u26a_rdqs.sp

ddr2控制器一些源码

*                          MICRON HSPICE MODEL
*
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*************************** 32Megx8 DDR2-400/533 SDRAM ************************
**************Example HSPICE setup file for RDQS and RDQS#*********************

***********************************************************
****           ____                                       *
****      IN--|    \                                      *
****          |     }------PAD--\/\/\/--@@@@--|--PKG_OUT  *
****   ENOUT--|____/             R_pkg  L_pkg |           *
****                                         ===C_pkg     *
****                                          |           *
****                                         GND          *
***********************************************************

**** This netlist is for the x8 256Mb DDR2-400/533 SDRAM *****************
**** The input signals are IN (input signal) and ENOUT (output enable signal).
**** The OUTPUT data is available on the signal PAD.
**** To account for package parasitics correlative impedance values
**** (netlist elements R_pkg, L_pkg, C_pkg) have been attached to the PAD
**** node.  The package output is on the signal PKG_OUT.

**** NOTE: This spice file is not designed to match datasheet timing numbers.
****       Delay times are smaller than those given in the data sheets.

**** The .LIB statement selects the following modes:
****    TT - Typical N, Typical P, Typical die capacitance
****    SS - Slow N, Slow P, Maximum die capacitance
****    FF - Fast N, Fast P, Minimum die capacitance

**** To run this simulation, the files "model.cnr" and "u26a_rdqsbuff.inc" are
**** required to be in the same directory as this netlist.
**** Temperature settings are: Typical 40C, Slow 100C, Fast 0C

.OPTIONS ACCT OPTS NOPAGE POST
.OPTIONS METHOD=GEAR
.OPTIONS SEARCH=' '  $This option must be present for decryption to work

.TRAN 0.05ns 10.0ns
**The temperature is for the slow case
.TEMP 100
.LIB "model.cnr" SS

**** Input signals and power supplies setup
**** Note: vccp is a regulated internal voltage
**** Match up typ, min, or max voltages for corner sims
.PARAM  vccq_typ  = 1.800V
.PARAM  vccq_min  = 1.700V
.PARAM  vccq_max  = 1.900V

.PARAM  vcc_typ   = 1.800V
.PARAM  vcc_min   = 1.700V
.PARAM  vcc_max   = 1.900V

.PARAM  vccp_typ  = 3.30V
.PARAM  vccp_min  = 3.20V
.PARAM  vccp_max  = 3.40V

.PARAM  gnd       = 0.0V
.PARAM  vssq      = 0.0V
********************************************************************************
.PARAM  vccq      = vccq_min
.PARAM  vcc       = vcc_min
.PARAM  vccp      = vccp_min
******************************************************************************** 
Vvccq   vccq  0  DC = vccq
Vvcc    vcc   0  DC = vcc
Vvccp   vccp  0  DC = vccp
Vvssq   vssq  0  DC = vssq
Vvtt    vtt   0  DC = 'vccq/2'

Vdrv fulldrv  0  DC = vcc  $vcc = 100%, gnd = 60%
**The fulldrv node selects between Full and Reduced output drive strengths.

*****************************************************************************
**On-Die Termination is controlled like the Extended Mode Register settings**
*****************************************************************************
**Bit Settings: EMR Bit 6     EMR Bit 2     Function    **
**                  0             0         disabled    **
**                  0             1         75 ohm ODT  **
**                  1             0         150 ohm ODT **
**                  1             1         50 ohm ODT  **
**********************************************************
Vodt_emr6  odt_emr6 0  DC = gnd  $ see table above for settings
Vodt_emr2  odt_emr2 0  DC = gnd  $ 0 = gnd, 1 = vcc
**********************************************************
Vodt_en    odt_en   0  DC = gnd
*Active high ODT enable, set odt_en to vcc/gnd and set the EMR bits to toggle ODT on/off

Ven    enout  0  DC = vcc
**Active high for output, Active low for Hi-Z (or ODT on if enabled)

Vin   in  0  PULSE gnd vcc 100ps 100ps 100ps 2.40ns 5.00ns
**Vin toggles the RDQS at 400Mb/s

* top cell:  rdqs
* *********************************************
* Output load circuits:
xi0 enout fulldrv in odt_emr2 odt_emr6 odt_en pad gnd vcc vccp vccq vssq u26a_rdqsbuff

* Refer to the IBIS model for specific package parasitic values.
r_pkg pad net1 R=56.5e-3
l_pkg net1 pkg_out L=1.96e-9
c_pkg pkg_out gnd c=270e-15

rload pkg_out vtt 25

.alter typ
.PARAM  vccq        = vccq_typ
.PARAM  vcc         = vcc_typ
.PARAM  vccp        = vccp_typ
.temp 40
.LIB "model.cnr" TT

.alter fast
.PARAM  vccq        = vccq_max
.PARAM  vcc         = vcc_max
.PARAM  vccp        = vccp_max
.temp 0
.LIB "model.cnr" FF

.END