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📄 u26a_dm.sp

📁 ddr2控制器一些源码
💻 SP
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*                          MICRON HSPICE MODEL
*
* Disclaimer:   This software code and all associated documentation, comments
*               or other information (collectively "Software") is provided 
*               "AS IS" without warranty of any kind. MICRON TECHNOLOGY, INC. 
*               ("MTI") EXPRESSLY DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED,
*               INCLUDING BUT NOT LIMITED TO, NONINFRINGEMENT OF THIRD PARTY
*               RIGHTS, AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
*               FOR ANY PARTICULAR PURPOSE. MTI DOES NOT WARRANT THAT THE
*               SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF
*               THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. FURTHERMORE,
*               MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR THE
*               RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
*               ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT
*               OF USE OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO
*               EVENT SHALL MTI, ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE
*               LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR
*               SPECIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS
*               OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION)
*               ARISING OUT OF YOUR USE OF OR INABILITY TO USE THE SOFTWARE,
*               EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*               Because some jurisdictions prohibit the exclusion or limitation
*               of liability for consequential or incidental damages, the above
*               limitation may not apply to you.
* 
*               Copyright 2005 Micron Technology, Inc. All rights reserved.
*
*************** 64Megx4, 32Megx8, 16Megx16 DDR2-400/533 SDRAM *****************
*******************Example HSPICE setup for DM input***************************

***********************************************************
****             ___                                      *
****            /  +|-----PAD---\/\/\/--@@@@-----IN_PKG   *
**** RCVR_OUT--{   -|-----VREF   R_pkg  L_pkg |           *
****            \___|--RCVREN                ===C_pkg     *
****                                          |           *
****                                         GND          *
***********************************************************

**** This netlist is for the x4, x8, x16 256Mb DDR2-400/533 SDRAM **********
**** The input signal is IN_PKG (input signal).
**** The output of the input receiver circuit is the node RCVR_OUT.
**** To account for package parasitics correlative impedance values
**** (netlist elements r_pkg,l_pkg,c_pkg) have been attached to the PAD node.

**** The .LIB statement selects the following modes:
****    TT - Typical N, Typical P, Typical die capacitance
****    SS - Slow N, Slow P, Maximum die capacitance
****    FF - Fast N, Fast P, Minimum die capacitance

**** To run this simulation, the files "model.cnr" and "u26a_dmbuff.inc" are
**** required to be in the same directory as this netlist.
**** Temperature settings are: Typical 40C, Slow 100C, Fast 0C

.OPTIONS ACCT OPTS NOPAGE POST
.OPTIONS METHOD=GEAR
.OPTIONS SEARCH=' '  $This option must be present for decryption to work

.TRAN 0.05ns 10.0ns
**The temperature is for the slow case
.TEMP 100
.LIB "model.cnr" SS

**** Input signals and power supplies setup
**** Note: vccp is a regulated internal voltage
**** Match up typ, min, or max voltages for corner sims
*****************************
.PARAM  vccq_typ  = 1.800V
.PARAM  vccq_min  = 1.700V
.PARAM  vccq_max  = 1.900V

.PARAM  vcc_typ   = 1.800V
.PARAM  vcc_min   = 1.700V
.PARAM  vcc_max   = 1.900V

.PARAM  vccp_typ  = 3.30V
.PARAM  vccp_min  = 3.20V
.PARAM  vccp_max  = 3.40V

.PARAM  gnd       = 0.0V
.PARAM  vssq      = 0.0V
********************************************************************************
.PARAM  vccq      = vccq_min
.PARAM  vcc       = vcc_min
.PARAM  vccp      = vccp_min
******************************************************************************** 
Vvccq   vccq  0  DC = vccq
Vvcc    vcc   0  DC = vcc
Vvccp   vccp  0  DC = vccp
Vvssq   vssq  0  DC = vssq
Vref    vref  0  DC = 'vccq/2' 

Ven   rcvr_en  0  DC = vcc
**Active high receiver enable

*****************************************************************************
**On-Die Termination is controlled like the Extended Mode Register settings**
*****************************************************************************
**Bit Settings: EMR Bit 6     EMR Bit 2     Function    **
**                  0             0         disabled    **
**                  0             1         75 ohm ODT  **
**                  1             0         150 ohm ODT **
**                  1             1         50 ohm ODT  **
**********************************************************
Vodt_emr6  odt_emr6 0  DC = gnd  $ see table above for settings
Vodt_emr2  odt_emr2 0  DC = gnd  $ 0 = gnd, 1 = vcc
**********************************************************
Vodt_en    odt_en   0  DC = gnd
*Active high ODT enable, set odt_en to vcc/gnd and set the EMR bits to toggle ODT on/off

Vin   in_pkg  0  PULSE gnd vccq 100ps 200ps 200ps 2.30ns 5.00ns
**Vin toggles the DM at 400Mb/s


* top cell:  dm
* *********************************************
* Output load circuits:
xi0 odt_emr2 odt_emr6 odt_en rcvr_en vref pad rcvr_out gnd vcc vccp vccq vssq u26a_dmbuff

* Refer to the IBIS model for specific package parasitic values.
r_pkg pad net1 R=56.5e-3
l_pkg net1 in_pkg L=1.96e-9
c_pkg in_pkg gnd c=270e-15


.alter typ
.PARAM  vccq        = vccq_typ
.PARAM  vcc         = vcc_typ
.PARAM  vccp        = vccp_typ
.temp 40
.LIB "model.cnr" TT

.alter fast
.PARAM  vccq        = vccq_max
.PARAM  vcc         = vcc_max
.PARAM  vccp        = vccp_max
.temp 0
.LIB "model.cnr" FF

.END

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