📄 nadia2.h

📁 at91sam9261 u-boot代码
💻 H
📖 第 1 页 / 共 5 页
字号:
	AT91_REG	 SYS_PIOD_MDSR; 	// Multi-driver Status Register	AT91_REG	 Reserved41[1]; 	// 	AT91_REG	 SYS_PIOD_PPUDR; 	// Pull-up Disable Register	AT91_REG	 SYS_PIOD_PPUER; 	// Pull-up Enable Register	AT91_REG	 SYS_PIOD_PPUSR; 	// Pull-up Status Register	AT91_REG	 Reserved42[1]; 	// 	AT91_REG	 SYS_PIOD_ASR; 	// Select A Register	AT91_REG	 SYS_PIOD_BSR; 	// Select B Register	AT91_REG	 SYS_PIOD_ABSR; 	// AB Select Status Register	AT91_REG	 Reserved43[9]; 	// 	AT91_REG	 SYS_PIOD_OWER; 	// Output Write Enable Register	AT91_REG	 SYS_PIOD_OWDR; 	// Output Write Disable Register	AT91_REG	 SYS_PIOD_OWSR; 	// Output Write Status Register	AT91_REG	 Reserved44[85]; 	// 	AT91_REG	 SYS_PIOE_PER; 	// PIO Enable Register	AT91_REG	 SYS_PIOE_PDR; 	// PIO Disable Register	AT91_REG	 SYS_PIOE_PSR; 	// PIO Status Register	AT91_REG	 Reserved45[1]; 	// 	AT91_REG	 SYS_PIOE_OER; 	// Output Enable Register	AT91_REG	 SYS_PIOE_ODR; 	// Output Disable Registerr	AT91_REG	 SYS_PIOE_OSR; 	// Output Status Register	AT91_REG	 Reserved46[1]; 	// 	AT91_REG	 SYS_PIOE_IFER; 	// Input Filter Enable Register	AT91_REG	 SYS_PIOE_IFDR; 	// Input Filter Disable Register	AT91_REG	 SYS_PIOE_IFSR; 	// Input Filter Status Register	AT91_REG	 Reserved47[1]; 	// 	AT91_REG	 SYS_PIOE_SODR; 	// Set Output Data Register	AT91_REG	 SYS_PIOE_CODR; 	// Clear Output Data Register	AT91_REG	 SYS_PIOE_ODSR; 	// Output Data Status Register	AT91_REG	 SYS_PIOE_PDSR; 	// Pin Data Status Register	AT91_REG	 SYS_PIOE_IER; 	// Interrupt Enable Register	AT91_REG	 SYS_PIOE_IDR; 	// Interrupt Disable Register	AT91_REG	 SYS_PIOE_IMR; 	// Interrupt Mask Register	AT91_REG	 SYS_PIOE_ISR; 	// Interrupt Status Register	AT91_REG	 SYS_PIOE_MDER; 	// Multi-driver Enable Register	AT91_REG	 SYS_PIOE_MDDR; 	// Multi-driver Disable Register	AT91_REG	 SYS_PIOE_MDSR; 	// Multi-driver Status Register	AT91_REG	 Reserved48[1]; 	// 	AT91_REG	 SYS_PIOE_PPUDR; 	// Pull-up Disable Register	AT91_REG	 SYS_PIOE_PPUER; 	// Pull-up Enable Register	AT91_REG	 SYS_PIOE_PPUSR; 	// Pull-up Status Register	AT91_REG	 Reserved49[1]; 	// 	AT91_REG	 SYS_PIOE_ASR; 	// Select A Register	AT91_REG	 SYS_PIOE_BSR; 	// Select B Register	AT91_REG	 SYS_PIOE_ABSR; 	// AB Select Status Register	AT91_REG	 Reserved50[9]; 	// 	AT91_REG	 SYS_PIOE_OWER; 	// Output Write Enable Register	AT91_REG	 SYS_PIOE_OWDR; 	// Output Write Disable Register	AT91_REG	 SYS_PIOE_OWSR; 	// Output Write Status Register	AT91_REG	 Reserved51[85]; 	// 	AT91_REG	 SYS_PMC_SCER; 	// System Clock Enable Register	AT91_REG	 SYS_PMC_SCDR; 	// System Clock Disable Register	AT91_REG	 SYS_PMC_SCSR; 	// System Clock Status Register	AT91_REG	 Reserved52[1]; 	// 	AT91_REG	 SYS_PMC_PCER; 	// Peripheral Clock Enable Register	AT91_REG	 SYS_PMC_PCDR; 	// Peripheral Clock Disable Register	AT91_REG	 SYS_PMC_PCSR; 	// Peripheral Clock Status Register	AT91_REG	 Reserved53[1]; 	// 	AT91_REG	 SYS_PMC_MOR; 	// Main Oscillator Register	AT91_REG	 SYS_PMC_MCFR; 	// Main Clock  Frequency Register	AT91_REG	 SYS_PMC_PLLAR; 	// PLL A Register	AT91_REG	 SYS_PMC_PLLBR; 	// PLL B Register	AT91_REG	 SYS_PMC_MCKR; 	// Master Clock Register	AT91_REG	 Reserved54[3]; 	// 	AT91_REG	 SYS_PMC_PCKR[8]; 	// Programmable Clock Register	AT91_REG	 SYS_PMC_IER; 	// Interrupt Enable Register	AT91_REG	 SYS_PMC_IDR; 	// Interrupt Disable Register	AT91_REG	 SYS_PMC_SR; 	// Status Register	AT91_REG	 SYS_PMC_IMR; 	// Interrupt Mask Register	AT91_REG	 Reserved55[36]; 	// 	AT91_REG	 SYS_RSTC_RCR; 	// Reset Control Register	AT91_REG	 SYS_RSTC_RSR; 	// Reset Status Register	AT91_REG	 SYS_RSTC_RMR; 	// Reset Mode Register	AT91_REG	 Reserved56[1]; 	// 	AT91_REG	 SYS_SHDWC_SHCR; 	// Shut Down Control Register	AT91_REG	 SYS_SHDWC_SHMR; 	// Shut Down Mode Register	AT91_REG	 SYS_SHDWC_SHSR; 	// Shut Down Status Register	AT91_REG	 Reserved57[1]; 	// 	AT91_REG	 SYS_RTTC0_RTMR; 	// Real-time Mode Register	AT91_REG	 SYS_RTTC0_RTAR; 	// Real-time Alarm Register	AT91_REG	 SYS_RTTC0_RTVR; 	// Real-time Value Register	AT91_REG	 SYS_RTTC0_RTSR; 	// Real-time Status Register	AT91_REG	 SYS_PITC_PIMR; 	// Period Interval Mode Register	AT91_REG	 SYS_PITC_PISR; 	// Period Interval Status Register	AT91_REG	 SYS_PITC_PIVR; 	// Period Interval Value Register	AT91_REG	 SYS_PITC_PIIR; 	// Period Interval Image Register	AT91_REG	 SYS_WDTC_WDCR; 	// Watchdog Control Register	AT91_REG	 SYS_WDTC_WDMR; 	// Watchdog Mode Register	AT91_REG	 SYS_WDTC_WDSR; 	// Watchdog Status Register	AT91_REG	 Reserved58[1]; 	// 	AT91_REG	 SYS_RTTC1_RTMR; 	// Real-time Mode Register	AT91_REG	 SYS_RTTC1_RTAR; 	// Real-time Alarm Register	AT91_REG	 SYS_RTTC1_RTVR; 	// Real-time Value Register	AT91_REG	 SYS_RTTC1_RTSR; 	// Real-time Status Register	AT91_REG	 SYS_GPBR[20]; 	// General Purpose Register} AT91S_SYS, *AT91PS_SYS;// -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register -------- #define AT91C_GPBR_GPRV       ((unsigned int) 0x0 <<  0) // (SYS) General Purpose Register Value// *****************************************************************************//              SOFTWARE API DEFINITION  FOR External Bus Interface 0// *****************************************************************************typedef struct _AT91S_EBI0 {	AT91_REG	 EBI0_DUMMY; 	// Dummy register - Do not use} AT91S_EBI0, *AT91PS_EBI0;// *****************************************************************************//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface// *****************************************************************************typedef struct _AT91S_SDRAMC {	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register} AT91S_SDRAMC, *AT91PS_SDRAMC;// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRAMC_MODE     ((unsigned int) 0xF <<  0) // (SDRAMC) Mode#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           ((unsigned int) 0x0) // (SDRAMC) Normal Mode#define 	AT91C_SDRAMC_MODE_NOP_CMD              ((unsigned int) 0x1) // (SDRAMC) Issue a NOP Command at every access#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          ((unsigned int) 0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access#define 	AT91C_SDRAMC_MODE_LMR_CMD              ((unsigned int) 0x3) // (SDRAMC) Issue a Load Mode Register at every access#define 	AT91C_SDRAMC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRAMC) Issue a Refresh#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          ((unsigned int) 0x5) // (SDRAMC) Issue an Extended Load Mode Register#define 	AT91C_SDRAMC_MODE_DEEP_CMD             ((unsigned int) 0x6) // (SDRAMC) Enter Deep Power Mode// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- #define AT91C_SDRAMC_COUNT    ((unsigned int) 0xFFF <<  0) // (SDRAMC) Refresh Counter// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRAMC_NC       ((unsigned int) 0x3 <<  0) // (SDRAMC) Number of Column Bits#define 	AT91C_SDRAMC_NC_8                    ((unsigned int) 0x0) // (SDRAMC) 8 Bits#define 	AT91C_SDRAMC_NC_9                    ((unsigned int) 0x1) // (SDRAMC) 9 Bits#define 	AT91C_SDRAMC_NC_10                   ((unsigned int) 0x2) // (SDRAMC) 10 Bits#define 	AT91C_SDRAMC_NC_11                   ((unsigned int) 0x3) // (SDRAMC) 11 Bits#define AT91C_SDRAMC_NR       ((unsigned int) 0x3 <<  2) // (SDRAMC) Number of Row Bits#define 	AT91C_SDRAMC_NR_11                   ((unsigned int) 0x0 <<  2) // (SDRAMC) 11 Bits#define 	AT91C_SDRAMC_NR_12                   ((unsigned int) 0x1 <<  2) // (SDRAMC) 12 Bits#define 	AT91C_SDRAMC_NR_13                   ((unsigned int) 0x2 <<  2) // (SDRAMC) 13 Bits#define AT91C_SDRAMC_NB       ((unsigned int) 0x1 <<  4) // (SDRAMC) Number of Banks#define 	AT91C_SDRAMC_NB_2_BANKS              ((unsigned int) 0x0 <<  4) // (SDRAMC) 2 banks#define 	AT91C_SDRAMC_NB_4_BANKS              ((unsigned int) 0x1 <<  4) // (SDRAMC) 4 banks#define AT91C_SDRAMC_CAS      ((unsigned int) 0x3 <<  5) // (SDRAMC) CAS Latency#define 	AT91C_SDRAMC_CAS_2                    ((unsigned int) 0x2 <<  5) // (SDRAMC) 2 cycles#define 	AT91C_SDRAMC_CAS_3                    ((unsigned int) 0x3 <<  5) // (SDRAMC) 3 cycles#define AT91C_SDRAMC_DBW      ((unsigned int) 0x1 <<  7) // (SDRAMC) Data Bus Width#define 	AT91C_SDRAMC_DBW_32_BITS              ((unsigned int) 0x0 <<  7) // (SDRAMC) 32 Bits datas bus#define 	AT91C_SDRAMC_DBW_16_BITS              ((unsigned int) 0x1 <<  7) // (SDRAMC) 16 Bits datas bus#define AT91C_SDRAMC_TWR      ((unsigned int) 0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles#define 	AT91C_SDRAMC_TWR_0                    ((unsigned int) 0x0 <<  8) // (SDRAMC) Value :  0#define 	AT91C_SDRAMC_TWR_1                    ((unsigned int) 0x1 <<  8) // (SDRAMC) Value :  1#define 	AT91C_SDRAMC_TWR_2                    ((unsigned int) 0x2 <<  8) // (SDRAMC) Value :  2#define 	AT91C_SDRAMC_TWR_3                    ((unsigned int) 0x3 <<  8) // (SDRAMC) Value :  3#define 	AT91C_SDRAMC_TWR_4                    ((unsigned int) 0x4 <<  8) // (SDRAMC) Value :  4#define 	AT91C_SDRAMC_TWR_5                    ((unsigned int) 0x5 <<  8) // (SDRAMC) Value :  5#define 	AT91C_SDRAMC_TWR_6                    ((unsigned int) 0x6 <<  8) // (SDRAMC) Value :  6#define 	AT91C_SDRAMC_TWR_7                    ((unsigned int) 0x7 <<  8) // (SDRAMC) Value :  7#define 	AT91C_SDRAMC_TWR_8                    ((unsigned int) 0x8 <<  8) // (SDRAMC) Value :  8#define 	AT91C_SDRAMC_TWR_9                    ((unsigned int) 0x9 <<  8) // (SDRAMC) Value :  9#define 	AT91C_SDRAMC_TWR_10                   ((unsigned int) 0xA <<  8) // (SDRAMC) Value : 10#define 	AT91C_SDRAMC_TWR_11                   ((unsigned int) 0xB <<  8) // (SDRAMC) Value : 11#define 	AT91C_SDRAMC_TWR_12                   ((unsigned int) 0xC <<  8) // (SDRAMC) Value : 12#define 	AT91C_SDRAMC_TWR_13                   ((unsigned int) 0xD <<  8) // (SDRAMC) Value : 13#define 	AT91C_SDRAMC_TWR_14                   ((unsigned int) 0xE <<  8) // (SDRAMC) Value : 14#define 	AT91C_SDRAMC_TWR_15                   ((unsigned int) 0xF <<  8) // (SDRAMC) Value : 15#define AT91C_SDRAMC_TRC      ((unsigned int) 0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles#define 	AT91C_SDRAMC_TRC_0                    ((unsigned int) 0x0 << 12) // (SDRAMC) Value :  0#define 	AT91C_SDRAMC_TRC_1                    ((unsigned int) 0x1 << 12) // (SDRAMC) Value :  1#define 	AT91C_SDRAMC_TRC_2                    ((unsigned int) 0x2 << 12) // (SDRAMC) Value :  2#define 	AT91C_SDRAMC_TRC_3                    ((unsigned int) 0x3 << 12) // (SDRAMC) Value :  3#define 	AT91C_SDRAMC_TRC_4                    ((unsigned int) 0x4 << 12) // (SDRAMC) Value :  4#define 	AT91C_SDRAMC_TRC_5                    ((unsigned int) 0x5 << 12) // (SDRAMC) Value :  5#define 	AT91C_SDRAMC_TRC_6                    ((unsigned int) 0x6 << 12) // (SDRAMC) Value :  6#define 	AT91C_SDRAMC_TRC_7                    ((unsigned int) 0x7 << 12) // (SDRAMC) Value :  7#define 	AT91C_SDRAMC_TRC_8                    ((unsigned int) 0x8 << 12) // (SDRAMC) Value :  8#define 	AT91C_SDRAMC_TRC_9                    ((unsigned int) 0x9 << 12) // (SDRAMC) Value :  9#define 	AT91C_SDRAMC_TRC_10                   ((unsigned int) 0xA << 12) // (SDRAMC) Value : 10#define 	AT91C_SDRAMC_TRC_11                   ((unsigned int) 0xB << 12) // (SDRAMC) Value : 11#define 	AT91C_SDRAMC_TRC_12                   ((unsigned int) 0xC << 12) // (SDRAMC) Value : 12
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -