📄 at_hw.h
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#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
// Maximum Frame Length Control Register
#define REG_MTU 0x149c
// Wake-On-Lan control register
#define REG_WOL_CTRL 0x14a0
#define WOL_PATTERN_EN 0x00000001
#define WOL_PATTERN_PME_EN 0x00000002
#define WOL_MAGIC_EN 0x00000004
#define WOL_MAGIC_PME_EN 0x00000008
#define WOL_LINK_CHG_EN 0x00000010
#define WOL_LINK_CHG_PME_EN 0x00000020
#define WOL_PATTERN_ST 0x00000100
#define WOL_MAGIC_ST 0x00000200
#define WOL_LINKCHG_ST 0x00000400
#define WOL_CLK_SWITCH_EN 0x00008000
#define WOL_PT0_EN 0x00010000
#define WOL_PT1_EN 0x00020000
#define WOL_PT2_EN 0x00040000
#define WOL_PT3_EN 0x00080000
#define WOL_PT4_EN 0x00100000
#define WOL_PT5_EN 0x00200000
#define WOL_PT6_EN 0x00400000
// WOL Length ( 2 DWORD )
#define REG_WOL_PATTERN_LEN 0x14a4
#define WOL_PT_LEN_MASK 0x7f
#define WOL_PT0_LEN_SHIFT 0
#define WOL_PT1_LEN_SHIFT 8
#define WOL_PT2_LEN_SHIFT 16
#define WOL_PT3_LEN_SHIFT 24
#define WOL_PT4_LEN_SHIFT 0
#define WOL_PT5_LEN_SHIFT 8
#define WOL_PT6_LEN_SHIFT 16
// Internal SRAM Partition Register
#define REG_SRAM_RFD_ADDR 0x1500
#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
#define SRAM_TCPH_ADDR_MASK 0x0fff
#define SRAM_TCPH_ADDR_SHIFT 0
#define SRAM_PATH_ADDR_MASK 0x0fff
#define SRAM_PATH_ADDR_SHIFT 16
// Load Ptr Register
#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
// Descriptor Control register
#define REG_DESC_BASE_ADDR_HI 0x1540
#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
#define DESC_RFD_RING_SIZE_MASK 0x7ff
#define DESC_RFD_RING_SIZE_SHIFT 0
#define DESC_RRD_RING_SIZE_MASK 0x7ff
#define DESC_RRD_RING_SIZE_SHIFT 16
#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
#define DESC_TPD_RING_SIZE_MASK 0x3ff
#define DESC_TPD_RING_SIZE_SHIFT 0
// TXQ Control Register
#define REG_TXQ_CTRL 0x1580
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
#define TXQ_CTRL_EN 0x20
#define TXQ_CTRL_ENH_MODE 0x40
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
// Jumbo packet Threshold for task offload
#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
#define TX_JUMBO_TASK_TH_MASK 0x7ff
#define TX_JUMBO_TASK_TH_SHIFT 0
#define TX_TPD_MIN_IPG_MASK 0x1f
#define TX_TPD_MIN_IPG_SHIFT 16
// RXQ Control Register
#define REG_RXQ_CTRL 0x15a0
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
#define RXQ_CTRL_EN 0x80000000
// Rx jumbo packet threshold and rrd retirement timer
#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
#define RXQ_JMBOSZ_TH_MASK 0x7ff
#define RXQ_JMBOSZ_TH_SHIFT 0
#define RXQ_JMBO_LKAH_MASK 0xf
#define RXQ_JMBO_LKAH_SHIFT 11
#define RXQ_RRD_TIMER_MASK 0xffff
#define RXQ_RRD_TIMER_SHIFT 16
// RFD flow control register
#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
// RRD flow control register
#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
// DMA Engine Control Register
#define REG_DMA_CTRL 0x15c0
#define DMA_CTRL_DMAR_IN_ORDER 0x1
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
#define DMA_CTRL_RCB_VALUE 0x8
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
#define DMA_CTRL_DMAR_EN 0x400
#define DMA_CTRL_DMAW_EN 0x800
// CMB/SMB Control Register
#define REG_CSMB_CTRL 0x15d0
#define CSMB_CTRL_CMB_NOW 1
#define CSMB_CTRL_SMB_NOW 2
#define CSMB_CTRL_CMB_EN 4
#define CSMB_CTRL_SMB_EN 8
// CMB DMA Write Threshold Register
#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
#define CMB_RRD_TH_SHIFT 0
#define CMB_RRD_TH_MASK 0x7ff
#define CMB_TPD_TH_SHIFT 16
#define CMB_TPD_TH_MASK 0x7ff
// RX/TX count-down timer to trigger CMB-write. 2us resolution.
#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
#define CMB_RX_TM_SHIFT 0
#define CMB_RX_TM_MASK 0xffff
#define CMB_TX_TM_SHIFT 16
#define CMB_TX_TM_MASK 0xffff
// Number of packet received since last CMB write
#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
// Number of packet transmitted since last CMB write
#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
// SMB auto DMA timer register
#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
// Mailbox Register
#define REG_MAILBOX 0x15f0
#define MB_RFD_PROD_INDX_SHIFT 0
#define MB_RFD_PROD_INDX_MASK 0x7ff
#define MB_RRD_CONS_INDX_SHIFT 11
#define MB_RRD_CONS_INDX_MASK 0x7ff
#define MB_TPD_PROD_INDX_SHIFT 22
#define MB_TPD_PROD_INDX_MASK 0x3ff
// Interrupt Status Register
#define REG_ISR 0x1600
#define ISR_SMB 1
#define ISR_TIMER 2
#define ISR_MANUAL 4
#define ISR_RXF_OV 8
#define ISR_RFD_UNRUN 0x10
#define ISR_RRD_OV 0x20
#define ISR_TXF_UNRUN 0x40
#define ISR_LINK 0x80
#define ISR_HOST_RFD_UNRUN 0x100
#define ISR_HOST_RRD_OV 0x200
#define ISR_DMAR_TO_RST 0x400
#define ISR_DMAW_TO_RST 0x800
#define ISR_GPHY 0x1000
#define ISR_RX_PKT 0x10000
#define ISR_TX_PKT 0x20000
#define ISR_TX_DMA 0x40000
#define ISR_RX_DMA 0x80000
#define ISR_CMB_RX 0x100000
#define ISR_CMB_TX 0x200000
#define ISR_MAC_RX 0x400000
#define ISR_MAC_TX 0x800000
#define ISR_UR_DETECTED 0x1000000
#define ISR_FERR_DETECTED 0x2000000
#define ISR_NFERR_DETECTED 0x4000000
#define ISR_CERR_DETECTED 0x8000000
#define ISR_PHY_LINKDOWN 0x10000000
#define ISR_DIS_SMB 0x20000000
#define ISR_DIS_DMA 0x40000000
#define ISR_DIS_INT 0x80000000
// Interrupt Mask Register
#define REG_IMR 0x1604
/* Normal Interrupt mask */
#define IMR_NORMAL_MASK (\
ISR_SMB | \
ISR_GPHY | \
ISR_PHY_LINKDOWN| \
ISR_DMAR_TO_RST | \
ISR_DMAW_TO_RST | \
ISR_CMB_TX | \
ISR_CMB_RX )
/* Debug Interrupt Mask (enable all interrupt) */
#define IMR_DEBUG_MASK (\
ISR_SMB | \
ISR_TIMER | \
ISR_MANUAL | \
ISR_RXF_OV | \
ISR_RFD_UNRUN | \
ISR_RRD_OV | \
ISR_TXF_UNRUN | \
ISR_LINK | \
ISR_CMB_TX | \
ISR_CMB_RX | \
ISR_RX_PKT | \
ISR_TX_PKT | \
ISR_MAC_RX | \
ISR_MAC_TX )
// Interrupt Status Register
#define REG_RFD_RRD_IDX 0x1800
#define REG_TPD_IDX 0x1804
/***************************** MII definition ***************************************/
/* PHY Common Register */
#define MII_BMCR 0x00
#define MII_BMSR 0x01
#define MII_PHYSID1 0x02
#define MII_PHYSID2 0x03
#define MII_ADVERTISE 0x04
#define MII_LPA 0x05
#define MII_EXPANSION 0x06
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