at_hw.h

Linux* Base Driver for the Attansic(R) L1 Gigabit Ethernet Adapter

/*
 * Module Name:
 *   at_hw.h
 *   
 * Abstract:
 *   structures , enums,  and macros for the MAC
 *
 * Revision History:
 *   Who             When        What
 * ------------------------------------------------
 *   Huangx      06-08-2004      created
 *
 * Notes:
*/

#ifndef _ATTANSIC_HW_H__
#define _ATTANSIC_HW_H__

#include "at_osdep.h"

#define _AT_ATTRIB_PACK_    __attribute__ ((packed))

struct at_adapter;
struct at_hw;

/* function prototype */

int32_t at_reset_hw(struct at_hw* hw);
int32_t at_read_mac_addr(struct at_hw* hw);
int32_t at_init_hw(struct at_hw* hw);
int32_t at_phy_setup_autoneg_adv(struct at_hw *hw);
int32_t at_phy_reset(struct at_hw *hw);
int32_t at_get_speed_and_duplex(struct at_hw *hw, uint16_t *speed, uint16_t *duplex);
//michael add 2005-11-17
int32_t at_set_speed_and_duplex(struct at_hw *hw, uint16_t speed, uint16_t duplex);
uint32_t at_auto_get_fc(struct at_adapter* adapter, uint16_t duplex);
uint32_t at_hash_mc_addr(struct at_hw *hw, uint8_t *mc_addr);
void at_hash_set(struct at_hw *hw, uint32_t hash_value);
int32_t at_read_phy_reg(struct at_hw *hw, uint16_t reg_addr, uint16_t *phy_data);
int32_t at_write_phy_reg(struct at_hw *hw, uint32_t reg_addr, uint16_t phy_data);
void at_read_pci_cfg(struct at_hw*  hw, uint32_t reg, uint16_t *value);
void at_write_pci_cfg(struct at_hw* hw, uint32_t reg, uint16_t *value); 
int32_t at_validate_mdi_setting(struct at_hw* hw);
int32_t at_setup_link(struct at_hw* hw);
void set_mac_addr(struct at_hw* hw);
int get_permanent_address(struct at_hw* hw);
boolean_t read_eeprom(struct at_hw* hw, uint32_t Offset, uint32_t* pValue);
void init_flash_opcode(struct at_hw* hw);
boolean_t spi_read(struct at_hw* hw, uint32_t addr, uint32_t* buf);
int32_t at_phy_enter_power_saving(struct at_hw* hw);
int32_t at_phy_leave_power_saving(struct at_hw* hw);

/* register definition */
#define REG_PCIE_CAP_LIST           0x58

#define REG_VPD_CAP                 0x6C
#define     VPD_CAP_ID_MASK                 0xff
#define     VPD_CAP_ID_SHIFT                0
#define     VPD_CAP_NEXT_PTR_MASK           0xFF
#define     VPD_CAP_NEXT_PTR_SHIFT          8
#define     VPD_CAP_VPD_ADDR_MASK           0x7FFF
#define     VPD_CAP_VPD_ADDR_SHIFT          16
#define     VPD_CAP_VPD_FLAG                0x80000000

#define REG_VPD_DATA                0x70

#define REG_SPI_FLASH_CTRL          0x200
#define     SPI_FLASH_CTRL_STS_NON_RDY      0x1
#define     SPI_FLASH_CTRL_STS_WEN          0x2
#define     SPI_FLASH_CTRL_STS_WPEN         0x80
#define     SPI_FLASH_CTRL_DEV_STS_MASK     0xFF
#define     SPI_FLASH_CTRL_DEV_STS_SHIFT    0
#define     SPI_FLASH_CTRL_INS_MASK         0x7
#define     SPI_FLASH_CTRL_INS_SHIFT        8
#define     SPI_FLASH_CTRL_START            0x800
#define     SPI_FLASH_CTRL_EN_VPD           0x2000
#define     SPI_FLASH_CTRL_LDSTART          0x8000
#define     SPI_FLASH_CTRL_CS_HI_MASK       0x3
#define     SPI_FLASH_CTRL_CS_HI_SHIFT      16
#define     SPI_FLASH_CTRL_CS_HOLD_MASK     0x3
#define     SPI_FLASH_CTRL_CS_HOLD_SHIFT    18
#define     SPI_FLASH_CTRL_CLK_LO_MASK      0x3
#define     SPI_FLASH_CTRL_CLK_LO_SHIFT     20
#define     SPI_FLASH_CTRL_CLK_HI_MASK      0x3
#define     SPI_FLASH_CTRL_CLK_HI_SHIFT     22
#define     SPI_FLASH_CTRL_CS_SETUP_MASK    0x3
#define     SPI_FLASH_CTRL_CS_SETUP_SHIFT   24
#define     SPI_FLASH_CTRL_EROM_PGSZ_MASK   0x3
#define     SPI_FLASH_CTRL_EROM_PGSZ_SHIFT  26
#define     SPI_FLASH_CTRL_WAIT_READY       0x10000000

#define REG_SPI_ADDR                0x204

#define REG_SPI_DATA                0x208

#define REG_SPI_FLASH_CONFIG        0x20C
#define     SPI_FLASH_CONFIG_LD_ADDR_MASK   0xFFFFFF
#define     SPI_FLASH_CONFIG_LD_ADDR_SHIFT  0
#define     SPI_FLASH_CONFIG_VPD_ADDR_MASK  0x3
#define     SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
#define     SPI_FLASH_CONFIG_LD_EXIST       0x4000000


#define REG_SPI_FLASH_OP_PROGRAM    0x210
#define REG_SPI_FLASH_OP_SC_ERASE   0x211
#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
#define REG_SPI_FLASH_OP_RDID       0x213
#define REG_SPI_FLASH_OP_WREN       0x214
#define REG_SPI_FLASH_OP_RDSR       0x215
#define REG_SPI_FLASH_OP_WRSR       0x216
#define REG_SPI_FLASH_OP_READ       0x217

#define REG_TWSI_CTRL               0x218
#define     TWSI_CTRL_LD_OFFSET_MASK        0xFF
#define     TWSI_CTRL_LD_OFFSET_SHIFT       0
#define     TWSI_CTRL_LD_SLV_ADDR_MASK      0x7
#define     TWSI_CTRL_LD_SLV_ADDR_SHIFT     8
#define     TWSI_CTRL_SW_LDSTART            0x800
#define     TWSI_CTRL_HW_LDSTART            0x1000
#define     TWSI_CTRL_SMB_SLV_ADDR_MASK     0x0x7F
#define     TWSI_CTRL_SMB_SLV_ADDR_SHIFT    15
#define     TWSI_CTRL_LD_EXIST              0x400000
#define     TWSI_CTRL_READ_FREQ_SEL_MASK    0x3
#define     TWSI_CTRL_READ_FREQ_SEL_SHIFT   23
#define     TWSI_CTRL_FREQ_SEL_100K         0
#define     TWSI_CTRL_FREQ_SEL_200K         1
#define     TWSI_CTRL_FREQ_SEL_300K         2
#define     TWSI_CTRL_FREQ_SEL_400K         3
#define     TWSI_CTRL_SMB_SLV_ADDR
#define     TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3
#define     TWSI_CTRL_WRITE_FREQ_SEL_SHIFT  24


#define REG_PCIE_DEV_MISC_CTRL      0x21C
#define     PCIE_DEV_MISC_CTRL_EXT_PIPE     0x2
#define     PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
#define     PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
#define     PCIE_DEV_MISC_CTRL_SERDES_ENDIAN    0x8
#define     PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN   0x10

// Selene Master Control Register
#define REG_MASTER_CTRL             0x1400
#define     MASTER_CTRL_SOFT_RST            0x1    
#define     MASTER_CTRL_MTIMER_EN           0x2 
#define     MASTER_CTRL_ITIMER_EN           0x4
#define     MASTER_CTRL_MANUAL_INT          0x8 
#define     MASTER_CTRL_REV_NUM_SHIFT       16     
#define     MASTER_CTRL_REV_NUM_MASK        0xff
#define     MASTER_CTRL_DEV_ID_SHIFT        24    
#define     MASTER_CTRL_DEV_ID_MASK         0xff

// Timer Initial Value Register
#define REG_MANUAL_TIMER_INIT       0x1404

// IRQ ModeratorTimer Initial Value Register
#define REG_IRQ_MODU_TIMER_INIT     0x1408      

#define REG_GPHY_ENABLE		    0x140C //w
// IRQ Anti-Lost Timer Initial Value Register
#define REG_CMBDISDMA_TIMER         0x140E      
// Block IDLE Status Register
#define REG_IDLE_STATUS             0x1410
#define     IDLE_STATUS_RXMAC               1  
#define     IDLE_STATUS_TXMAC               2 
#define     IDLE_STATUS_RXQ                 4  
#define     IDLE_STATUS_TXQ                 8 
#define     IDLE_STATUS_DMAR                0x10       
#define     IDLE_STATUS_DMAW                0x20      
#define     IDLE_STATUS_SMB                 0x40     
#define     IDLE_STATUS_CMB                 0x80    

// MDIO Control Register
#define REG_MDIO_CTRL               0x1414
#define     MDIO_DATA_MASK                  0xffff 
#define     MDIO_DATA_SHIFT                 0     
#define     MDIO_REG_ADDR_MASK              0x1f 
#define     MDIO_REG_ADDR_SHIFT             16
#define     MDIO_RW                         0x200000     
#define     MDIO_SUP_PREAMBLE               0x400000   
#define     MDIO_START                      0x800000   
#define     MDIO_CLK_SEL_SHIFT              24
#define     MDIO_CLK_25_4                   0
#define     MDIO_CLK_25_6                   2
#define     MDIO_CLK_25_8                   3
#define     MDIO_CLK_25_10                  4
#define     MDIO_CLK_25_14                  5
#define     MDIO_CLK_25_20                  6
#define     MDIO_CLK_25_28                  7
#define     MDIO_BUSY                       0x8000000       
#define     MDIO_WAIT_TIMES                 30        
                  
// MII PHY Status Register
#define REG_PHY_STATUS              0x1418                   

// BIST Control and Status Register0 (for the Packet Memory)
#define REG_BIST0_CTRL              0x141c                   
#define     BIST0_NOW                       0x1       
#define     BIST0_SRAM_FAIL                 0x2    
#define     BIST0_FUSE_FLAG                 0x4  
#define REG_BIST1_CTRL              0x1420                   
#define     BIST1_NOW                       0x1        
#define     BIST1_SRAM_FAIL                 0x2        
#define     BIST1_FUSE_FLAG                 0x4
                                                            
// MAC Control Register                         
#define REG_MAC_CTRL                0x1480                  
#define     MAC_CTRL_TX_EN                  1   
#define     MAC_CTRL_RX_EN                  2    
#define     MAC_CTRL_TX_FLOW                4     
#define     MAC_CTRL_RX_FLOW                8      
#define     MAC_CTRL_LOOPBACK               0x10    
#define     MAC_CTRL_DUPLX                  0x20     
#define     MAC_CTRL_ADD_CRC                0x40       
#define     MAC_CTRL_PAD                    0x80      
#define     MAC_CTRL_LENCHK                 0x100       
#define     MAC_CTRL_HUGE_EN                0x200        
#define     MAC_CTRL_PRMLEN_SHIFT           10            
#define     MAC_CTRL_PRMLEN_MASK            0xf                 
#define     MAC_CTRL_RMV_VLAN               0x4000        
#define     MAC_CTRL_PROMIS_EN              0x8000       
#define     MAC_CTRL_TX_PAUSE               0x10000    
#define     MAC_CTRL_SCNT                   0x20000   
#define     MAC_CTRL_SRST_TX                0x40000        
#define     MAC_CTRL_TX_SIMURST             0x80000       
#define     MAC_CTRL_SPEED_SHIFT            20           
#define     MAC_CTRL_SPEED_MASK             0x300000
#define     MAC_CTRL_SPEED_1000             2
#define     MAC_CTRL_SPEED_10_100           1
#define     MAC_CTRL_DBG_TX_BKPRESURE       0x400000    
#define     MAC_CTRL_TX_HUGE                0x800000   
#define     MAC_CTRL_RX_CHKSUM_EN           0x1000000 
#define     MAC_CTRL_MC_ALL_EN              0x2000000           
#define     MAC_CTRL_BC_EN                  0x4000000      
#define     MAC_CTRL_DBG                    0x8000000     

// MAC IPG/IFG Control Register                 
#define REG_MAC_IPG_IFG             0x1484                   
#define     MAC_IPG_IFG_IPGT_SHIFT          0            
#define     MAC_IPG_IFG_IPGT_MASK           0x7f
#define     MAC_IPG_IFG_MIFG_SHIFT          8           
#define     MAC_IPG_IFG_MIFG_MASK           0xff       
#define     MAC_IPG_IFG_IPGR1_SHIFT         16        
#define     MAC_IPG_IFG_IPGR1_MASK          0x7f     
#define     MAC_IPG_IFG_IPGR2_SHIFT         24      
#define     MAC_IPG_IFG_IPGR2_MASK          0x7f

// MAC STATION ADDRESS                          
#define REG_MAC_STA_ADDR            0x1488

// Hash table for multicast address
#define REG_RX_HASH_TABLE           0x1490

// MAC Half-Duplex Control Register 
#define REG_MAC_HALF_DUPLX_CTRL     0x1498                   
#define     MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0     
#define     MAC_HALF_DUPLX_CTRL_LCOL_MASK    0x3ff
#define     MAC_HALF_DUPLX_CTRL_RETRY_SHIFT  12   
#define     MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf
#define     MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000         
#define     MAC_HALF_DUPLX_CTRL_NO_BACK_C    0x20000   
#define     MAC_HALF_DUPLX_CTRL_NO_BACK_P    0x40000