at_hw.c

Linux* Base Driver for the Attansic(R) L1 Gigabit Ethernet Adapter

#include "at.h"
#ifdef SIOCGMIIPHY
#include <linux/mii.h>
#endif

/* 
 * The little-endian AUTODIN II ethernet CRC calculations.
 * A big-endian version is also available.
 * This is slow but compact code.  Do not use this routine 
 * for bulk data, use a table-based routine instead.
 * This is common code and should be moved to net/core/crc.c.
 * Chips may use the upper or lower CRC bits, and may reverse 
 * and/or invert them.  Select the endian-ness that results 
 * in minimal calculations.
 */
uint32_t
ether_crc_le(int length, unsigned char *data)
{
    uint32_t crc = ~0;  /* Initial value. */
    while(--length >= 0) {
        unsigned char current_octet = *data++;
        int bit;
        for (bit = 8; --bit >= 0; current_octet >>= 1) {
            if ((crc ^ current_octet) & 1) {
                crc >>= 1;
                crc ^= 0xedb88320;
            } 
            else
                crc >>= 1;
        }
    }
    return ~crc;
}

/********************************************************************
* Reset the transmit and receive units; mask and clear all interrupts.
* 
* hw - Struct containing variables accessed by shared code
* return : AT_SUCCESS  or  idle status (if error)
********************************************************************/
int32_t
at_reset_hw(struct at_hw *hw)
{
    uint32_t icr;
    uint16_t pci_cfg_cmd_word;
    int i;

    DEBUGFUNC("at_reset_hw");

    /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
    at_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
    if ((pci_cfg_cmd_word&
           (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER))
        != (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
        pci_cfg_cmd_word |= 
           (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
        at_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
    }


    /* Clear Interrupt mask to stop board from generating
     * interrupts & Clear any pending interrupt events 
     */
//    AT_WRITE_REG(hw, REG_IMR, 0);
//    AT_WRITE_REG(hw, REG_ISR, 0xffffffff);

    /* Issue Soft Reset to the MAC.  This will reset the chip's
     * transmit, receive, DMA.  It will not effect
     * the current PCI configuration.  The global reset bit is self-
     * clearing, and should clear within a microsecond.
     */
    AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
    wmb();

    AT_WRITE_REGW(hw, REG_GPHY_ENABLE, 1);

    msec_delay(1); // delay about 1ms 

    /* Wait at least 10ms for All module to be Idle 
     */
    for (i=0; i < 10; i++)
    {
        icr = AT_READ_REG(hw, REG_IDLE_STATUS);
        if (!icr)
            break;
        msec_delay(1); // delay 1 ms
        cpu_relax();
    }

    if (icr) 
    {
        DEBUGOUT("MAC state machine cann't be idle since disabled for 10ms second\n");
        return icr;
    }

    return AT_SUCCESS;
}


/*********************************************************************
* Reads the adapter's MAC address from the EEPROM 
*
* hw - Struct containing variables accessed by shared code
*********************************************************************/
int32_t
at_read_mac_addr(struct at_hw * hw)
{
    uint16_t  i;
    
    DEBUGFUNC("at_read_mac_addr");
    
    if (get_permanent_address(hw)) {
        // for test
        hw->perm_mac_addr[0] = 0x00;
        hw->perm_mac_addr[1] = 0x13;
        hw->perm_mac_addr[2] = 0x74;
        hw->perm_mac_addr[3] = 0x00;
        hw->perm_mac_addr[4] = 0x5c;
        hw->perm_mac_addr[5] = 0x38;
    } 
    
    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
        hw->mac_addr[i] = hw->perm_mac_addr[i];
    return AT_SUCCESS;
}

/*********************************************************************
* Hashes an address to determine its location in the multicast table
*
* hw - Struct containing variables accessed by shared code
* mc_addr - the multicast address to hash
*********************************************************************/
/* 
 * at_hash_mc_addr
 *  purpose
 *      set hash value for a multicast address
 *      hash calcu processing :
 *          1. calcu 32bit CRC for multicast address
 *          2. reverse crc with MSB to LSB
 */
uint32_t
at_hash_mc_addr(
        struct at_hw *hw,
        uint8_t *mc_addr)
{
    uint32_t crc32, value=0;
    int i;

    crc32 = ether_crc_le(6, mc_addr);
    crc32 = ~crc32;
    for (i=0; i<32; i++)
    {
        value |= (((crc32>>i)&1)<<(31-i));
    }

    return value;
}


/********************************************************************
* Sets the bit in the multicast table corresponding to the hash value.
*
* hw - Struct containing variables accessed by shared code
* hash_value - Multicast address hash value
********************************************************************/
void
at_hash_set(
            struct at_hw *hw, 
            uint32_t hash_value)
{
    uint32_t hash_bit, hash_reg;
    uint32_t mta;
    
    /* The HASH Table  is a register array of 2 32-bit registers.
    * It is treated like an array of 64 bits.  We want to set
    * bit BitArray[hash_value]. So we figure out what register
    * the bit is in, read it, OR in the new bit, then write
    * back the new value.  The register is determined by the
    * upper 7 bits of the hash value and the bit within that
    * register are determined by the lower 5 bits of the value.
    */
    hash_reg = (hash_value >> 31) & 0x1;
    hash_bit = (hash_value >> 26) & 0x1F;
    
    mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
    
    mta |= (1 << hash_bit);
    
    AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
}

/********************************************************************
* Make L001's PHY out of Power Saving State (bug)
*
* hw - Struct containing variables accessed by shared code
* when power on, L001's PHY always on Power saving State
* (Gigabit Link forbidden)
********************************************************************/

int32_t
at_phy_leave_power_saving(struct at_hw* hw)
{
    
    int32_t ret;

//        DEBUGFUNC("at_phy_leave_power_saving!");
 
    
    if ((ret = at_write_phy_reg(hw, 29, 0x0029)))
        return ret;
    
        return at_write_phy_reg(hw, 30, 0);
}

int32_t
at_phy_enter_power_saving(struct at_hw* hw)
{
//    int32_t ret_val;
//    uint16_t phy_data;
    
    DEBUGFUNC("at_phy_enter_power_saving");
/*    
    ret_val = at_write_phy_reg(hw, ...);
    ret_val = at_write_phy_reg(hw, ...);
    ....
*/
    return AT_SUCCESS;
}

/********************************************************************
* Performs basic configuration of the adapter.
*
* hw - Struct containing variables accessed by shared code
* Assumes that the controller has previously been reset and is in a
* post-reset uninitialized state. Initializes multicast table, 
* and  Calls routines to setup link
* Leaves the transmit and receive units disabled and uninitialized.
********************************************************************/
int32_t
at_init_hw(struct at_hw *hw)
{
    uint32_t ret_val = 0;
    
    DEBUGFUNC("at_init_hw");
    
    /* Zero out the Multicast HASH table */
//    DEBUGOUT("Zeroing the MTA");
    /* clear the old settings from the multicast hash table */
    AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
    AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
    
    init_flash_opcode(hw);
    
    
    if (!hw->phy_configured) {
        DEBUGOUT("configure phy now !");

          /* enable GPHY LinkChange Interrrupt */
          ret_val = at_write_phy_reg(hw, 18, 0xC00);
      if (ret_val)        
              return ret_val;
    
          /* make PHY out of power-saving state */
              
          ret_val = at_phy_leave_power_saving(hw);
          if (ret_val)
              return ret_val;
          
        /* Call a subroutine to configure the link */
        ret_val = at_setup_link(hw);
    } 
    DEBUGOUT1("at_init_hw: ret: %d", ret_val);

    return ret_val;
}   


/********************************************************************
* Configures link settings.
*
* hw - Struct containing variables accessed by shared code
* Assumes the hardware has previously been reset and the
* transmitter and receiver are not enabled.
********************************************************************/
int32_t
at_setup_link(struct at_hw *hw)
{
    int32_t ret_val;
    
    DEBUGFUNC("at_setup_link");
    
    /* Options:
     *  PHY will advertise value(s) parsed from
     *  autoneg_advertised and fc
     *  no matter what autoneg is , We will not wait link result.
     */
    
    ret_val = at_phy_setup_autoneg_adv(hw);
    if(ret_val) {
        DEBUGOUT("Error Setting up Auto-Negotiation");
        return ret_val;
    }
    
    /* SW.Reset , En-Auto-Neg if needed */
    DEBUGOUT("Restarting Auto-Neg");
    ret_val = at_phy_reset(hw);
    if (ret_val) {
        DEBUGOUT("Error Resetting the phy");
        return ret_val;
    }

    hw->phy_configured = TRUE;
    
    return ret_val;
}


/******************************************************************************
* Detects the current speed and duplex settings of the hardware.
*
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*****************************************************************************/
int32_t
at_get_speed_and_duplex(
        struct at_hw *hw,
        uint16_t *speed,
        uint16_t *duplex)
{
    int32_t ret_val;
    uint16_t phy_data;

//    DEBUGFUNC("at_get_speed_and_duplex");

    // ; --- Read   PHY Specific Status Register (17)
    ret_val = at_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
    if (ret_val)
        return ret_val;
    
    if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
        return AT_ERR_PHY_RES;
    
    switch(phy_data&MII_AT001_PSSR_SPEED) {
    case MII_AT001_PSSR_1000MBS :
        *speed = SPEED_1000;
//        DEBUGOUT("1000 Mbs, ");
        break;
    case MII_AT001_PSSR_100MBS:
        *speed = SPEED_100;
//        DEBUGOUT("100 Mbs, ");
        break;
    case MII_AT001_PSSR_10MBS:
        *speed = SPEED_10;
//        DEBUGOUT("10 Mbs, ");
        break;
    default:
        DEBUGOUT("Error Speed !\n");
        return AT_ERR_PHY_SPEED;
        break;
    }
    
    if (phy_data & MII_AT001_PSSR_DPLX) {
        *duplex = FULL_DUPLEX;
//        DEBUGOUT("Full Duplex");
    } else {
        *duplex = HALF_DUPLEX;
//        DEBUGOUT(" Half Duplex");
    }

    return AT_SUCCESS;
}

/*********************************************************************
* Reads the value from a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
*********************************************************************/
int32_t
at_read_phy_reg(
            struct at_hw *hw,
            uint16_t reg_addr,
            uint16_t *phy_data)
{
    uint32_t val;
    int i;
    
//    DEBUGFUNC("at_read_phy_reg");

    val = ((uint32_t)(reg_addr&MDIO_REG_ADDR_MASK)) 
                << MDIO_REG_ADDR_SHIFT |
            MDIO_START |
            MDIO_SUP_PREAMBLE |
            MDIO_RW |
            MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
    AT_WRITE_REG(hw, REG_MDIO_CTRL, val);

    wmb();
    
    for (i=0; i<MDIO_WAIT_TIMES; i++) {
        usec_delay(2);
        val = AT_READ_REG(hw, REG_MDIO_CTRL);
        if (!(val&(MDIO_START|MDIO_BUSY))) {
            break;
        }
        wmb();
    }
    if (!(val&(MDIO_START|MDIO_BUSY))) {
        *phy_data = (uint16_t)val;
        return AT_SUCCESS; 
    }   

    return AT_ERR_PHY;
}

/********************************************************************
* Writes a value to a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
********************************************************************/
int32_t
at_write_phy_reg(
        struct at_hw *hw,
        uint32_t reg_addr,
        uint16_t phy_data)
{
    int i;
    uint32_t val;
    
    val =   ((uint32_t)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
            (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
            MDIO_SUP_PREAMBLE |
            MDIO_START |
            MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
    AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
//    printk(KERN_INFO "phy write 0x%x <- 0x%x\n", reg_addr, phy_data);
//    DEBUGOUT1("phy write 0x%x <- 0x%x, value = 0x%x", i
//              reg_addr, 
//              phy_data, 
//              val);
    
    wmb();
    
    for (i=0; i<MDIO_WAIT_TIMES; i++) {
        usec_delay(2);
        val = AT_READ_REG(hw, REG_MDIO_CTRL);
        if (!(val&(MDIO_START|MDIO_BUSY))) {
            break;
        }
        wmb();
    }

    if (!(val&(MDIO_START|MDIO_BUSY)))
        return AT_SUCCESS;

    return AT_ERR_PHY;
}

/********************************************************************
* Configures PHY autoneg and flow control advertisement settings
*
* hw - Struct containing variables accessed by shared code
********************************************************************/
int32_t
at_phy_setup_autoneg_adv(struct at_hw *hw)
{