at_osdep.h

Linux* Base Driver for the Attansic(R) L1 Gigabit Ethernet Adapter

#ifndef _ATTANSIC_OS_DEP_H_
#define _ATTANSIC_OS_DEP_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include "kcompat.h"

#define usec_delay(x)	udelay(x)
#ifndef msec_delay
#define msec_delay(x)	do { if(in_interrupt()) { \
			/* Don't mdelay in interrupt context!*/ \
				BUG(); \
			} else { \
				msleep(x); \
			}} while(0)
/* Some workarounds require millisecond delays and are run during interrupt
 * context.  Most notably, when establishing link, the phy may need tweaking
 * but cannot process phy register reads/writes faster than millisecond
 * intervals...and we establish link due to a "link status change" interrupt.
 */
#define msec_delay_irq(x) mdelay(x)
#endif

#define PCI_COMMAND_REGISTER	PCI_COMMAND
#define CMD_MEM_WRT_INVALIDATE	PCI_COMMAND_INVALIDATE

typedef enum {
#undef FALSE
	FALSE = 0,
#undef TRUE
	TRUE = 1
} boolean_t;



#ifdef DBG
#define DEBUGOUT(S)		printk(KERN_DEBUG S "\n")
#define DEBUGOUT1(S, A...)	printk(KERN_DEBUG S "\n", A)
#else
#define DEBUGOUT(S)
#define DEBUGOUT1(S, A...)
#endif

#define DEBUGFUNC(F) DEBUGOUT(F)
#define DEBUGOUT2 DEBUGOUT1
#define DEBUGOUT3 DEBUGOUT2
#define DEBUGOUT7 DEBUGOUT3


#define AT_WRITE_REG(a, reg, value) ( \
    writel((value), ((a)->hw_addr + reg)))

#define AT_READ_REG(a, reg) ( \
    readl((a)->hw_addr + reg ))
    
    
#define AT_WRITE_REGB(a, reg, value) (\
    writeb((value), ((a)->hw_addr + reg)))

#define AT_READ_REGB(a, reg) (\
    readb((a)->hw_addr + reg))

#define AT_WRITE_REGW(a, reg, value) (\
    writew((value), ((a)->hw_addr + reg)))
    
#define AT_READ_REGW(a, reg) (\
    readw((a)->hw_addr + reg))

#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
    writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))

#define AT_READ_REG_ARRAY(a, reg, offset) ( \
    readl(((a)->hw_addr + reg) + ((offset) << 2)))


#endif//_ATTANSIC_OS_DEP_H_