adsp-21161.ldf

2005 Center for Biological & Computational Learning at MIT and MIT All rights reserved. Permissio

ARCHITECTURE(ADSP-21161)

//
// ADSP-21161 Memory Map:
//   ------------------------------------------------
//   Internal memory  0x0000 0000 to 0x000f ffff
//   ------------------------------------------------
//                    0x0000 0000 to 0x0001 ffff  IOP Regs
//           Block 0  0x0002 0000 to 0x0002 1fff  Long Word (64) Addresses
//                    0x0002 2000 to 0x0002 7fff  (reserved)
//           Block 1  0x0002 8000 to 0x0002 9fff  Long Word (64) Addresses
//                    0x0002 a000 to 0x0003 ffff  (reserved)
//           Block 0  0x0004 0000 to 0x0004 3fff  Normal Word (32/48) Addresses
//                    0x0004 4000 to 0x0004 ffff  (reserved)
//           Block 1  0x0005 0000 to 0x0005 3fff  Normal Word (32/48) Addresses
//                    0x0005 4000 to 0x0007 ffff  (reserved)
//           Block 0  0x0008 0000 to 0x0008 7fff  Short Word (16) Addresses
//                    0x0008 8000 to 0x0009 ffff  (reserved)
//           Block 1  0x000a 0000 to 0x000a 7fff  Short Word (16) Addresses
//                    0x000a 8000 to 0x000f ffff  (reserved)
//   ------------------------------------------------
//   Multiproc memory 0x0010 0000 to 0x007f ffff
//   ------------------------------------------------
//                    0x0010 0000 to 0x0011 ffff  2116x ID=001 Internal memory
//                    0x0012 0000 to 0x0013 ffff  2116x ID=010 Internal memory
//                    0x0014 0000 to 0x0015 ffff  2116x ID=011 Internal memory
//                    0x0016 0000 to 0x0017 ffff  2116x ID=100 Internal memory
//                    0x0018 0000 to 0x0019 ffff  2116x ID=101 Internal memory
//                    0x001a 0000 to 0x001b ffff  2116x ID=110 Internal memory
//                    0x001c 0000 to 0x001f ffff  2116x ID=all Internal memory
//   ------------------------------------------------
//   External memory  0x0020 0000 to 0xffff ffff
//   ------------------------------------------------
//
// This architecture file allocates:
//         Internal 256 words of run-time header in memory block 0
//                  256 words of initialization code in memory block 0
//                   6K words of C code space in memory block 0
//                 1.5K words of C PM data space in memory block 0
//                   8K words of C DM data space in memory block 1
//                   4K words of C heap space in memory block 1
//                   4K words of C stack space in memory block 1

SEARCH_DIR( $ADI_DSP\211xx\lib )

#ifdef _ADI_THREADS
$LIBRARIES = libc161mt.dlb, libiomt.dlb, libdsp160.dlb;
#else
$LIBRARIES = libc161.dlb, libio.dlb, libdsp160.dlb;
#endif

// Libraries from the command line are included in COMMAND_LINE_OBJECTS.

$OBJECTS = $COMMAND_LINE_OBJECTS;

MEMORY
{
	//40000 - 400ff is the inturrupt table (vector table)
	mem_rth  { TYPE(PM RAM) START(0x00040000) END(0x000400ff) WIDTH(48) }	
	mem_init { TYPE(PM RAM) START(0x00040100) END(0x000401ff) WIDTH(48) }	
	mem_pmco { TYPE(PM RAM) START(0x00040200) END(0x000419ff) WIDTH(48) }
	mem_pmda { TYPE(PM RAM) START(0x00042700) END(0x00043fff) WIDTH(32) }
	mem_dmda { TYPE(DM RAM) START(0x00050000) END(0x00053fff) WIDTH(32) } // the gap between 43fff and 50000 is reserved (not sure why but it is)
	mem_dmex { TYPE(DM RAM) START(0x00200000) END(0x002f42f0) WIDTH(32) }
}

//Declare  Multiprocessor Memory Space (MMS) offset values for processors ID1 and ID2 
MPMEMORY
{	
	ID1 { START(0x00100000) }  
	ID2 { START(0x00120000) }
}

//Declare external shared memory 
SHARED_MEMORY
{
	OUTPUT(shared.sm)
	SECTIONS
	{	dxe_dmex
		{ 
			INPUT_SECTIONS( shared.doj(sram_da) )
		} >mem_dmex
	}
}

PROCESSOR ID1		// Processor ID1 sections definition. 
{   
	LINK_AGAINST(shared.sm,ID2.dxe)
    OUTPUT(ID1.dxe)
    
	SECTIONS
    {
   		dxe_rth
		{ 
			INPUT_SECTIONS( ID1.doj(seg_rth) $LIBRARIES(seg_rth))
		} >mem_rth

		dxe_pmco
		{ 
			INPUT_SECTIONS( ID1.doj(seg_pmco) $LIBRARIES(seg_pmco))
		} >mem_pmco

		dxe_pmda
		{ 
			INPUT_SECTIONS( ID1.doj(seg_pmda) $LIBRARIES(seg_pmda))
		} >mem_pmda

		dxe_dmda
		{ 
			INPUT_SECTIONS( ID1.doj(seg_dmda) $LIBRARIES(seg_dmda))
		} >mem_dmda
	}
}

PROCESSOR ID2		// Processor ID2 sections definition.
{
	LINK_AGAINST(shared.sm,ID1.dxe)
    OUTPUT(ID2.dxe)
    
	SECTIONS
    {
   		dxe_rth
		{
	 		INPUT_SECTIONS( ID2.doj(seg_rth) $LIBRARIES(seg_rth))
		} >mem_rth

		dxe_pmco
		{ 
			INPUT_SECTIONS( ID2.doj(seg_pmco) $LIBRARIES(seg_pmco))
		} >mem_pmco

		dxe_pmda
		{
			INPUT_SECTIONS( ID2.doj(seg_pmda) $LIBRARIES(seg_pmda))
		} >mem_pmda

		dxe_dmda
		{
			INPUT_SECTIONS( ID2.doj(seg_dmda) $LIBRARIES(seg_dmda))
		} >mem_dmda

	}
}

/*
PROCESSOR p0
{
    LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

    SECTIONS
    {
		// .text output section
		seg_rth
		{
			INPUT_SECTIONS( $OBJECTS(seg_rth) $LIBRARIES(seg_rth))
		} >seg_rth

		seg_init
		{
			ldf_seginit_space = . ;
			INPUT_SECTIONS( $OBJECTS(seg_init) $LIBRARIES(seg_init))
		} >seg_init

		seg_pmco
		{
			INPUT_SECTIONS( $OBJECTS(seg_pmco) $LIBRARIES(seg_pmco))
		} >seg_pmco

		seg_pmda
		{
			INPUT_SECTIONS( $OBJECTS(seg_pmda) $LIBRARIES(seg_pmda))
		} >seg_pmda

		seg_dmda
		{
			INPUT_SECTIONS( $OBJECTS(seg_dmda) $LIBRARIES(seg_dmda))
		} > seg_dmda

    }
}*/