📄 def21161.h
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#define DMA2ST 0x00000002 /* DMA channel 2 (RX1A/TX1A) Active Status */
#define DMA4ST 0x00000004 /* DMA channel 4 (RX2A/TX2A) Active Status */
#define DMA6ST 0x00000008 /* DMA channel 6 (RX3A/TX3A) Active Status */
#define DMA8ST 0x00000010 /* DMA channel 8 (LBUF0) Active Status */
#define DMA9ST 0x00000020 /* DMA channel 9 (LBUF1) Active Status */
#define DMA1ST 0x00000040 /* DMA channel 1 (RX0B/TX0B) Active Status */
#define DMA3ST 0x00000080 /* DMA channel 3 (RX1B/TX1B) Active Status */
#define DMA5ST 0x00000100 /* DMA channel 5 (RX2B/TX2B) Active Status */
#define DMA7ST 0x00000200 /* DMA channel 7 (RX3B/TX3B) Active Status */
#define DMA10ST 0x00000400 /* DMA channel 10 (EPB0) Active Status */
#define DMA11ST 0x00000800 /* DMA channel 11 (EPB1) Active Status */
#define DMA12ST 0x00001000 /* DMA channel 12 (EPB2) Active Status */
#define DMA13ST 0x00002000 /* DMA channel 13 (EPB3) Active Status */
#define DMA0CHST 0x00010000 /* DMA channel 0 (RX0A/TX0A) Chaining Status */
#define DMA2CHST 0x00020000 /* DMA channel 2 (RX1A/TX1A) Chaining Status */
#define DMA4CHST 0x00040000 /* DMA channel 4 (RX2A/TX2A) Chaining Status */
#define DMA6CHST 0x00080000 /* DMA channel 6 (RX3A/TX3A) Chaining Status */
#define DMA8CHST 0x00100000 /* DMA channel 8 (LBUF0) Chaining Status */
#define DMA9CHST 0x00200000 /* DMA channel 9 (LBUF1) Chaining Status */
#define DMA1CHST 0x00400000 /* DMA channel 1 (RX0B/TX0B) Chaining Status */
#define DMA3CHST 0x00800000 /* DMA channel 3 (RX1B/TX1B) Chaining Status */
#define DMA5CHST 0x01000000 /* DMA channel 5 (RX2B/TX2B) Chaining Status */
#define DMA7CHST 0x02000000 /* DMA channel 7 (RX3B/TX3B) Chaining Status */
#define DMA10CHST 0x04000000 /* DMA channel 10 (EPB0) Chaining Status */
#define DMA11CHST 0x08000000 /* DMA channel 11 (EPB1) Chaining Status */
#define DMA12CHST 0x10000000 /* DMA channel 12 (EPB2) Chaining Status */
#define DMA13CHST 0x20000000 /* DMA channel 13 (EPB3) Chaining Status */
/* SDCTL - SDRAM Control Register bit definitions */
#define SDCL1 0x00000001 /* SDCL[1:0] - CAS Latency field */
#define SDCL2 0x00000002 /* (delay between RD cmd and data at o/p pins) */
#define SDCL3 0x00000003 /* configurable between 1 and 3 SDCLK cycles */
#define DSDCTL 0x00000004 /* disable SDCLK0, /RAS, /CAS & SDCKE pins */
#define DSDCK1 0x00000008 /* disable SDCLK1 pin */
#define SDTRAS0 0x00000000 /* SDTRAS[3:0] - tRAS spec (active command delay)*/
#define SDTRAS1 0x00000010 /* (required delay between a Bank Activate */
#define SDTRAS2 0x00000020 /* command to a Precharge command) */
#define SDTRAS3 0x00000030 /* configurable between 0 to 15 SDCLK cycles */
#define SDTRAS4 0x00000040
#define SDTRAS5 0x00000050
#define SDTRAS6 0x00000060
#define SDTRAS7 0x00000070
#define SDTRAS8 0x00000080
#define SDTRAS9 0x00000090
#define SDTRAS10 0x000000a0
#define SDTRAS11 0x000000b0
#define SDTRAS12 0x000000c0
#define SDTRAS13 0x000000d0
#define SDTRAS14 0x000000e0
#define SDTRAS15 0x000000f0
#define SDTRP0 0x00000000 /* SDTRP[2:0] - tRP spec (precharge delay) */
#define SDTRP1 0x00000100 /* (required delay between a precharge command */
#define SDTRP2 0x00000200 /* to a Bank Activate command) */
#define SDTRP3 0x00000300 /* configurable between 1 to 7 cycles */
#define SDTRP4 0x00000400
#define SDTRP5 0x00000500
#define SDTRP6 0x00000600
#define SDTRP7 0x00000700
#define SDPM 0x00000800 /* SDRAM power-up mode bit */
#define SDPGS256 0x00000000 /* SDRAM Page Size - 256 words */
#define SDPGS512 0x00001000 /* SDRAM Page Size - 512 words */
#define SDPGS1024 0x00002000 /* SDRAM Page Size - 1024 words */
#define SDPGS2048 0x00003000 /* SDRAM Page Size - 2048 words */
#define SDPSS 0x00004000 /* SDRAM power-up sequence start command */
#define SDSRF 0x00008000 /* Self refresh command */
#define SDEM0 0x00010000 /* Memory Bank 0 SDRAM Enable */
#define SDEM1 0x00020000 /* Memory Bank 1 SDRAM Enable */
#define SDEM2 0x00040000 /* Memory Bank 2 SDRAM Enable */
#define SDEM3 0x00080000 /* Memory Bank 3 SDRAM Enable */
#define SDBN2 0x00000000 /* SDRAM contains 2 memory banks */
#define SDBN4 0x00100000 /* SDRAM contains 4 memory banks */
#define SDCKRx1 0x00200000 /* 1:1 (full) SDCLK-to-CCLK (core-clock) ratio */
#define SDCKR_DIV2 0x00000000 /* 1:2 (one-half) SDCLK-to-CCLK ratio */
#define SDBUF 0x00800000 /* Pipeline (reg. buf) option */
#define SDTRCD0 0x00000000 /* SDTRCD[2:0] - tRCD spec. (RAS-to-CAS delay) */
#define SDTRCD1 0x01000000 /* (required delay between a Bank Activate cmd */
#define SDTRCD2 0x02000000 /* and the start of the first RD or WR) */
#define SDTRCD3 0x03000000 /* configurable between 1 to 7 SDCLK cycles */
#define SDTRCD4 0x04000000
#define SDTRCD5 0x05000000
#define SDTRCD6 0x06000000
#define SDTRCD7 0x07000000
/* IOFLAG - programmable I/O status macro definitions */
#define FLG4 0x00000001 /* FLAG4 value (Low = '0', High = '1') */
#define FLG5 0x00000002 /* FLAG5 value (Low = '0', High = '1') */
#define FLG6 0x00000004 /* FLAG6 value (Low = '0', High = '1') */
#define FLG7 0x00000008 /* FLAG7 value (Low = '0', High = '1') */
#define FLG8 0x00000010 /* FLAG8 value (Low = '0', High = '1') */
#define FLG9 0x00000020 /* FLAG9 value (Low = '0', High = '1') */
#define FLG10 0x00000040 /* FLAG10 value (Low = '0', High = '1') */
#define FLG11 0x00000080 /* FLAG11 value (Low = '0', High = '1') */
/* IOFLAG - programmable I/O control macro definitions */
#define FLG4O 0x00000100 /* FLAG4 control ('0' = flag input, '1' = flag output) */
#define FLG5O 0x00000200 /* FLAG5 control ('0' = flag input, '1' = flag output) */
#define FLG6O 0x00000400 /* FLAG6 control ('0' = flag input, '1' = flag output) */
#define FLG7O 0x00000800 /* FLAG7 control ('0' = flag input, '1' = flag output) */
#define FLG8O 0x00001000 /* FLAG8 control ('0' = flag input, '1' = flag output) */
#define FLG9O 0x00002000 /* FLAG9 control ('0' = flag input, '1' = flag output) */
#define FLG10O 0x00004000 /* FLAG10 control ('0' = flag input, '1' = flag output) */
#define FLG11O 0x00008000 /* FLAG11 control ('0' = flag input, '1' = flag output) */
/*SPICTL register */
#define SPIEN 0x00000001 /* SPI system enable */
#define SPRINT 0x00000002 /* SPIRX buffer interrupt enable */
#define SPTINT 0x00000004 /* SPITX buffer interrupt enable */
#define MS 0x00000008 /* Master/Slave Mode bit */
#define CP 0x00000010 /* SPICLK Polarity */
#define CPHASE 0x00000020 /* SPICLK Phase */
#define DF 0x00000040 /* Data Format */
#define WL8 0x00000000 /* SPI Word Length = 8 */
#define WL16 0x00000080 /* SPI Word Length = 16 */
#define WL32 0x00000180 /* SPI Word Length = 32 */
#define BAUDR0 0x00000000 /* BAUDRATE = CCLK / 2**(2 + 0) = CCLK/4 */
#define BAUDR1 0x00000200 /* BAUDRATE = CCLK / 2**(2 + 1) = CCLK/8 */
#define BAUDR2 0x00000400 /* BAUDRATE = CCLK / 2**(2 + 2) = CCLK/16 */
#define BAUDR3 0x00000600 /* BAUDRATE = CCLK / 2**(2 + 3) = CCLK/32 */
#define BAUDR4 0x00000800 /* BAUDRATE = CCLK / 2**(2 + 4) = CCLK/64 */
#define BAUDR5 0x00000A00 /* BAUDRATE = CCLK / 2**(2 + 5) = CCLK/128 */
#define BAUDR6 0x00000C00 /* BAUDRATE = CCLK / 2**(2 + 6) = CCLK/512 */
#define BAUDR7 0x00000E00 /* BAUDRATE = CCLK / 2**(2 + 7) = CCLK/1024 */
#define BAUDR8 0x00001000 /* BAUDRATE = CCLK / 2**(2 + 8) = CCLK/2048 */
#define BAUDR9 0x00001200 /* BAUDRATE = CCLK / 2**(2 + 9) = CCLK/4096 */
#define BAUDR10 0x00001400 /* BAUDRATE = CCLK / 2**(2 + 10) = CCLK/8192 */
#define BAUDR11 0x00001600 /* BAUDRATE = CCLK / 2**(2 + 11) = CCLK/16384 */
#define BAUDR12 0x00001800 /* BAUDRATE = CCLK / 2**(2 + 12) = CCLK/32768 */
#define BAUDR13 0x00001A00 /* BAUDRATE = CCLK / 2**(2 + 13) = CCLK/65536 */
#define BAUDR14 0x00001C00 /* BAUDRATE = CCLK / 2**(2 + 14) = CCLK/131072 */
#define BAUDR15 0x00001E00 /* BAUDRATE = CCLK / 2**(2 + 15) = CCLK/262144 */
#define TDMAEN 0x00002000 /* SPITX transmit buffer DMA enable, DMA channel 9 */
#define PSSE 0x00004000 /* Programmable slave device select */
#define FLS0 0x00008000 /* FLAG0 slave device select enable */
#define FLS1 0x00010000 /* FLAG1 slave device select enable */
#define FLS2 0x00020000 /* FLAG2 slave device select enable */
#define FLS3 0x00040000 /* FLAG3 slave device select enable */
#define SMLS 0x00080000 /* Seamless operation */
#define DCPH0 0x00100000 /* Select or deselect SPIDS~ between transfers */
#define DMISO 0x02000000 /* Disable MISO Pin for Broadcast Mode */
#define OPD 0x04000000 /* Open drain output enable for data pins */
#define RDMAEN 0x08000000 /* SPIRX recevie buffer DMA enable, DMA channel 8 */
#define PACKEN 0x10000000 /* 8-to-16 Bit Packing Enable */
#define SGN 0x20000000 /* Sign-extend SPIRX/SPITX data */
#define SENDZ 0x40000000 /* Send zero or repeat previous data when SPITX empty */
#define GM 0x80000000 /* Retrieve or discard incoming data when SPIRX full */
/* SPISTAT register */
#define SPIF 0x00000001 /* SPI transmit or receive transfer complete */
#define MME 0x00000002 /* Multimaster error */
#define TXE 0x00000004 /* SPITX transmission error (underflow) */
#define TXS0 0x00000008 /* TXS[0] - SPITX data buffer status */
#define TXS1 0x00000010 /* TXS[1] - SPITX data buffer status */
#define RBSY 0x00000020 /* SPIRX reception error (overflow) */
#define RXS0 0x00000040 /* RXS[0] - SPIRX data buffer status */
#define RXS1 0x00000080 /* RXS[1] - SPIRX data buffer status */
/* LCTL register - 0xcc */
#define L0EN 0x00000001 /* Link buffer 0 enable */
#define L0DEN 0x00000002 /* Link buffer 0 DMA enable */
#define L0CHEN 0x00000004 /* Link buffer 0 DMA chaining enable */
#define L0TRAN 0x00000008 /* Link buffer 0 data direction */
#define L0EXT 0x00000010 /* Link buffer 0 extended word size */
#define L0CLKD0 0x00000020 /* L0CLKD[0] Link buffer 0 CCLK divide ratio */
#define L0CLKD1 0x00000040 /* L0CLKD[1] Link buffer 0 CCLK divide ratio */
#define L0PDRDE 0x00000100 /* Link Port 0 pulldown resister disable */
#define L0DPWID 0x00000200 /* Link buffer 0 data path width */
#define L1EN 0x00000400 /* Link buffer 1 enable */
#define L1DEN 0x00000800 /* Link buffer 1 DMA enable */
#define L1CHEN 0x00001000 /* Link buffer 1 DMA chaining enable */
#define L1TRAN 0x00002000 /* Link buffer 1 data direction */
#define L1EXT 0x00004000 /* Link buffer 1 extended word size */
#define L1CLKD0 0x00008000 /* L1CLKD[0] Link buffer 1 CCLK divide ratio */
#define L1CLKD1 0x00010000 /* L1CLKD[1] Link buffer 1 CCLK divide ratio */
#define L1PDRDE 0x00040000 /* Link Port 1 pulldown resister disable */
#define L1DPWID 0x00080000 /* Link buffer 1 data path width */
#define A0LB 0x00100000 /* Link Port Assignment for LBUF0 - 2106x/21160 compatibility */
#define A1LB 0x00200000 /* Link Port Assignment for LBUF1 - 2106x/21160 compatibility */
#define LAB0 0x00100000 /* Link Port Assignment for LBUF0 - new naming conventions */
#define LAB1 0x00200000 /* Link Port Assignment for LBUF1 - new naming conventions */
#define L0STAT0 0x00400000 /* L0STAT[0] - link buffer 0 status (read-only) */
#define L0STAT1 0x00800000 /* L0STAT[1] - link buffer 0 status (read-only) */
#define L1STAT0 0x01000000 /* L1STAT[0] - link buffer 1 status (read-only) */
#define L1STAT1 0x02000000 /* L1STAT[1] - link buffer 1 status (read-only) */
#define LRERR0 0x04000000 /* Link Buffer 0 receive pack error status */
#define LRERR1 0x08000000 /* Link Buffer 1 receive pack error status */
/* SP02MCTL & SP13MCTL registers */
#define MCE 0x00000001 /* Multichannel Mode Enable */
#define MFD0 0x00000000 /* no frame delay, multichannel FS pulse in same SCLK cycle as first data bit */
#define MFD1 0x00000002 /* multichannel mode 1 cycle frame sync delay */
#define MFD2 0x00000004 /* multichannel mode 2 cycle frame sync delay */
#define MFD3 0x00000006 /* multichannel mode 3 cycle frame sync delay */
#define MFD4 0x00000008 /* multichannel mode 4 cycle frame sync delay */
#define MFD5 0x0000000A /* multichannel mode 5 cycle frame sync delay */
#define MFD6 0x0000000C /* multichannel mode 6 cycle frame sync delay */
#define MFD7 0x0000000E /* multichannel mode 7 cycle frame sync delay */
#define MFD8 0x00000010 /* multichannel ⌨️ 快捷键说明
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