📄 def21161.h
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#define IM11 0x49 /* Internal DMA11 memory access modifier */
#define C11 0x4a /* Contains number of DMA11 transfers remaining */
#define CP11 0x4b /* Points to next DMA11 parameters */
#define GP11 0x4c /* DMA11 General purpose */
#define EI11 0x4d /* External DMA11 address */
#define EM11 0x4e /* External DMA11 address modifier */
#define EC11 0x4f /* External DMA counter */
#define II12 0x50 /* Internal DMA12 memory address */
#define IM12 0x51 /* Internal DMA12 memory access modifier */
#define C12 0x52 /* Contains number of DMA12 transfers remaining */
#define CP12 0x53 /* Points to next DMA12 parameters */
#define GP12 0x54 /* DMA12 General purpose */
#define EI12 0x55 /* External DMA12 address */
#define EM12 0x56 /* External DMA12 address modifier */
#define EC12 0x57 /* External DMA12 counter */
#define II13 0x58 /* Internal DMA13 memory address */
#define IM13 0x59 /* Internal DMA13 memory access modifier */
#define C13 0x5a /* Contains number of DMA13 transfers remaining */
#define CP13 0x5b /* Points to next DMA13 parameters */
#define GP13 0x5c /* DMA13 General purpose */
#define EI13 0x5d /* External DMA13 address */
#define EM13 0x5e /* External DMA13 address modifier */
#define EC13 0x5f /* External DMA13 counter */
/* Emulation/Breakpoint Registers (remapped from UREG space) */
/* NOTES:
- These registers are ONLY accessible by the core
- It is *highly* recommended that these facilities be accessed only
through the ADI emulator routines
*/
/* Core Emulation HWBD Registers */
#define PSA1S 0xa0 /* Instruction address start #1 */
#define PSA1E 0xa1 /* Instruction address end #1 */
#define PSA2S 0xa2 /* Instruction address start #2 */
#define PSA2E 0xa3 /* Instruction address end #2 */
#define PSA3S 0xa4 /* Instruction address start #3 */
#define PSA3E 0xa5 /* Instruction address end #3 */
#define PSA4S 0xa6 /* Instruction address start #4 */
#define PSA4E 0xa7 /* Instruction address end #4 */
#define PMDAS 0xa8 /* Program Data address start */
#define PMDAE 0xa9 /* Program Data address end */
#define DMA1S 0xaa /* Data address start #1 */
#define DMA1E 0xab /* Data address end #1 */
#define DMA2S 0xac /* Data address start #2 */
#define DMA2E 0xad /* Data address end #2 */
#define EMUN 0xae /* hwbp hit-count register */
/* IOP Emulation HWBP Bounds Registers */
#define IOAS 0xb0 /* IOA Upper Bounds Register */
#define IOAE 0xb1 /* IOA Lower Bounds Register */
#define EPAS 0xb2 /* EPA Upper Bounds Register */
#define EPAE 0xb3 /* EPA Lower Bounds Register */
/*----------------------------------------------------------------------------*/
/* */
/* IOP Control/Status Register Bit Definitions */
/* */
/*----------------------------------------------------------------------------*/
/* SYSCON Register */
#define SRST 0x00000001 /* Soft Reset */
#define BSO 0x00000002 /* Boot Select Override */
#define IIVT 0x00000004 /* Internal Interrupt Vector Table */
#define IWT 0x00000008 /* Instruction word transfer (0 = data, 1 = inst) */
#define HBW32 0x00000000 /* Host bus width: 32 */
#define HBW16 0x00000010 /* Host bus width: 16 */
#define HBW8 0x00000020 /* Host bus width: 8 */
#define HMSWF 0x00000080 /* Host packing order (0 = LSW first, 1 = MSW) */
#define HPFLSH 0x00000100 /* Host pack flush */
#define IMDW0X 0x00000200 /* Internal memory block 0, extended data (40 bit) */
#define IMDW1X 0x00000400 /* Internal memory block 1, extended data (40 bit) */
#define ADREDY 0x00000800 /* Active Drive Ready */
#define BHD 0x00010000 /* Buffer Hand Disable */
#define EBPR00 0x00000000 /* External bus priority: Even */
#define EBPR01 0x00020000 /* External bus priority: Core has priority */
#define EBPR10 0x00040000 /* External bus priority: IO has priority */
#define DCPR 0x00080000 /* Select rotating access priority on DMA10 - DMA13 */
#define LDCPR 0x00100000 /* Select rotating access priority on DMA8 - DMA9 */
#define PRROT 0x00200000 /* Select rotating prio between LPort and EPort */
#define COD 0x00400000 /* Clock Out Disable */
#define IPACK0 0x40000000 /* External instruction execution packing mode bit 0 */
#define IPACK1 0x80000000 /* External instruction execution packing mode bit 1 */
/* SYSTAT Register */
#define HSTM 0x00000001 /* Host is the Bus Master */
#define BSYN 0x00000002 /* Bus arbitration logic is synchronized */
#define CRBM 0x00000070 /* Current ADSP211xx Bus Master */
#define IDC 0x00000700 /* ADSP211xx ID Code */
#define VIPD 0x00002000 /* Vector interrupt pending (1 = pending) */
#define CRAT 0x00070000 /* CLK_CFG(3-0), Core:CLKIN clock ratio */
#define SSWPD 0x00100000 /* Sync slave write pending... SSWPD bit added for 21161 */
#define SWPD 0x00200000 /* Any (sync + Async) slave write pending */
#define HPS 0x01c00000 /* Host pack status... HPS modified for 21161 */
/* MODE2_SHDW Register - IOP register adrees 0x11 */
/* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 01010
bits 29-28 are silicon revision[1:0], read only, value: 01
These former MODE2 register bitfields (only) are now routed to the MODE2
Shadow register (IOP register 0x11). Bits 25-31 now reserved in MODE2. */
#define PID20 0x0E000000 /* PID[2:0] Processor Identification (read-only) */
#define SIREV 0x30000000 /* Silicon Revision (read-only) */
#define PID43 0xC0000000 /* PID[4:3] Processor Identification (read-only) */
/* WAIT Register */
/* generic WAIT bitfields */
#define EB0AM 0x00000003 /* External Bank 0 Access Mode */
#define EB0WS 0x0000001C /* External Bank 0 Waitstate Configuration */
#define EB1AM 0x00000060 /* External Bank 1 Access Mode */
#define EB1WS 0x00000380 /* External Bank 1 Waitstate Configuration */
#define EB2AM 0x00000C00 /* External Bank 1 Access Mode */
#define EB2WS 0x00007000 /* External Bank 2 Waitstate Configuration */
#define EB3AM 0x00018000 /* External Bank 1 Access Mode */
#define EB3WS 0x000E0000 /* External Bank 3 Waitstate Configuration */
#define RBAM 0x00300000 /* ROM Boot Access Mode */
#define RBWS 0x01C00000 /* ROM Boot Waitstate Configuration */
#define HIDMA 0x80000000 /* Single idle cycle for DMA handshake */
/* specific wait access mode settings */
#define EB0A0 0x00000000 /* Ext Bank 0 Async, internal AND external ACK */
#define EB0S1 0x00000001 /* Ext Bank 0 Sync, 2-cycle reads, 1-cycle writes */
#define EB0S2 0x00000002 /* Ext Bank 0 Sync, 2-cycle reads, 2-cycle writes */
#define EB1A0 0x00000000 /* Ext Bank 1 Async, internal AND external ACK */
#define EB1S1 0x00000020 /* Ext Bank 1 Sync, 2-cycle reads, 1-cycle writes */
#define EB1S2 0x00000040 /* Ext Bank 1 Sync, 2-cycle reads, 2-cycle writes */
#define EB2A0 0x00000000 /* Ext Bank 2 Async, internal AND external ACK */
#define EB2S1 0x00000400 /* Ext Bank 2 Sync, 2-cycle reads, 1-cycle writes */
#define EB2S2 0x00000800 /* Ext Bank 2 Sync, 2-cycle reads, 2-cycle writes */
#define EB3A0 0x00000000 /* Ext Bank 3 Async, internal AND external ACK */
#define EB3S1 0x00008000 /* Ext Bank 3 Sync, 2-cycle reads, 1-cycle writes */
#define EB3S2 0x00010000 /* Ext Bank 3 Sync, 2-cycle reads, 2-cycle writes */
#define RBWA0 0x00000000 /* ROM boot: Async, internal AND external ACK */
#define RBWS1 0x00100000 /* ROM boot: Sync, 2-cycle reads, 1-cycle writes */
#define RBWS2 0x00200000 /* ROM boot: Sync, 2-cycle reads, 2-cycle writes */
/* individual waitstate combinations */
#define EB0WS0 0x00000000 /* External Bank 0: 0 waitstates, no hold cycle */
#define EB0WS1 0x00000004 /* External Bank 0: 1 waitstates, no hold cycle */
#define EB0WS2 0x00000008 /* External Bank 0: 2 waitstates, hold cycle */
#define EB0WS3 0x0000000C /* External Bank 0: 3 waitstates, hold cycle */
#define EB0WS4 0x00000010 /* External Bank 0: 4 waitstates, hold cycle */
#define EB0WS5 0x00000014 /* External Bank 0: 5 waitstates, hold cycle */
#define EB0WS6 0x00000018 /* External Bank 0: 6 waitstates, hold cycle */
#define EB0WS7 0x0000001C /* External Bank 0: 7 waitstates, hold cycle */
#define EB1WS0 0x00000000 /* External Bank 1: 0 waitstates, no hold cycle */
#define EB1WS1 0x00000080 /* External Bank 1: 1 waitstates, no hold cycle */
#define EB1WS2 0x00000100 /* External Bank 1: 2 waitstates, hold cycle */
#define EB1WS3 0x00000180 /* External Bank 1: 3 waitstates, hold cycle */
#define EB1WS4 0x00000200 /* External Bank 1: 4 waitstates, hold cycle */
#define EB1WS5 0x00000280 /* External Bank 1: 5 waitstates, hold cycle */
#define EB1WS6 0x00000300 /* External Bank 1: 6 waitstates, hold cycle */
#define EB1WS7 0x00000380 /* External Bank 1: 7 waitstates, hold cycle */
#define EB2WS0 0x00000000 /* External Bank 2: 0 waitstates, no hold cycle */
#define EB2WS1 0x00001000 /* External Bank 2: 1 waitstates, no hold cycle */
#define EB2WS2 0x00002000 /* External Bank 2: 2 waitstates, hold cycle */
#define EB2WS3 0x00003000 /* External Bank 2: 3 waitstates, hold cycle */
#define EB2WS4 0x00004000 /* External Bank 2: 4 waitstates, hold cycle */
#define EB2WS5 0x00005000 /* External Bank 2: 5 waitstates, hold cycle */
#define EB2WS6 0x00006000 /* External Bank 2: 6 waitstates, hold cycle */
#define EB2WS7 0x00007000 /* External Bank 2: 7 waitstates, hold cycle */
#define EB3WS0 0x00000000 /* External Bank 3: 0 waitstates, no hold cycle */
#define EB3WS1 0x00020000 /* External Bank 3: 1 waitstates, no hold cycle */
#define EB3WS2 0x00040000 /* External Bank 3: 2 waitstates, hold cycle */
#define EB3WS3 0x00060000 /* External Bank 3: 3 waitstates, hold cycle */
#define EB3WS4 0x00080000 /* External Bank 3: 4 waitstates, hold cycle */
#define EB3WS5 0x000A0000 /* External Bank 3: 5 waitstates, hold cycle */
#define EB3WS6 0x000C0000 /* External Bank 3: 6 waitstates, hold cycle */
#define EB3WS7 0x000E0000 /* External Bank 3: 7 waitstates, hold cycle */
#define RBWST0 0x00000000 /* ROM boot wait state 0, no hold cycle */
#define RBWST1 0x00400000 /* ROM boot wait state 1, no hold cycle */
#define RBWST2 0x00800000 /* ROM boot wait state 2, hold cycle */
#define RBWST3 0x00C00000 /* ROM boot wait state 3, hold cycle */
#define RBWST4 0x01000000 /* ROM boot wait state 4, hold cycle */
#define RBWST5 0x01400000 /* ROM boot wait state 5, hold cycle */
#define RBWST6 0x01800000 /* ROM boot wait state 6, hold cycle */
#define RBWST7 0x01C00000 /* ROM boot wait state 7, hold cycle */
/* DMAC10, DMAC11, DMAC12, DMAC13 Register Bitfield Definitions */
#define DEN 0x00000001 /* External Port DMA Enable */
#define CHEN 0x00000002 /* External Port DMA Chaining Enable */
#define TRAN 0x00000004 /* External Port EPBx Transmit/Receive Select */
#define DTYPE 0x00000020 /* EPBx FIFO Buffer Data Type Select */
#define PMODE1 0x00000040 /* EPBx FIFO Packing Modes... 16-bit external to 32/64-bit internal packing */
#define PMODE2 0x00000080 /* 16-bit external to 48-bit internal packing */
#define PMODE3 0x000000C0 /* 32-bit external to 48-bit internal packing */
#define PMODE4 0x00000100 /* No Pack Mode - 32-bit external to 32/64-bit internal packing */
#define PMODE5 0x00000140 /* 8-bit external to 48-bit internal packing */
#define PMODE6 0x00000180 /* 8-bit external to 32/64-bit internal packing */
#define MSWF 0x00000200 /* Most Significant Word First During Packing */
#define MASTER 0x00000400 /* EPBx DMA Master Mode Enable */
#define HSHAKE 0x00000800 /* EPBx DMA Handshake Mode Enable */
#define INTIO 0x00001000 /* Single Word Interrupts for EPBx FIFO Buffers */
#define EXTERN 0x00002000 /* External Handshake Mode Enable */
#define FLSH 0x00004000 /* Flush EPBx FIFO Buffers and Status */
#define PRIO 0x00008000 /* External Port Bus Priority Access */
#define FS 0x00030000 /* External Port FIFO Buffer Status (read-only) */
#define INT32 0x00040000 /* Internal Memory 32-bit Transfer Select */
#define MAXBL0 0x00080000 /* Maximum Burst Length Select Disabled */
#define MAXBL1 0x00100000 /* Maximum Burst Length Limit of 4 Enabled */
#define PS 0x00E00000 /* External Port EPBx FIFO Buffer Packing Status (read-only) */
/* DMASTAT Register (read-only) */
#define DMA0ST 0x00000001 /* DMA channel 0 (RX0A/TX0A) Active Status */
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