def21161.h

2005 Center for Biological & Computational Learning at MIT and MIT All rights reserved. Permissio

/*------ DMA Parameter Register Assignments - New Naming Conventions -------*/

/* DMA Channel 0 - Serial Port 0, A channel data */
#define II0A    0x60	   /* Internal DMA0 memory address		      		*/
#define IM0A    0x61	   /* Internal DMA0 memory access modifier	      	*/
#define C0A     0x62	   /* Contains number of DMA0 transfers remaining   */
#define CP0A    0x63	   /* Points to next DMA0 parameters		      	*/
#define GP0A    0x64	   /* DMA0 General purpose		      				*/

/* DMA Channel 1 - Serial Port 0, B channel data */
#define II0B    0x80	   /* Internal DMA1 memory address		      		*/
#define IM0B    0x81	   /* Internal DMA1 memory access modifier	      	*/
#define C0B     0x82	   /* Contains number of DMA1 transfers remaining   */
#define CP0B    0x83	   /* Points to next DMA1 parameters		      	*/
#define GP0B    0x84	   /* DMA1 General purpose		      				*/

/* DMA Channel 2 - Serial Port 1, A channel data */
#define II1A    0x68	   /* Internal DMA2 memory address		      		*/
#define IM1A    0x69	   /* Internal DMA2 memory access modifier	      	*/
#define C1A     0x6a	   /* Contains number of DMA2 transfers remaining   */
#define CP1A    0x6b	   /* Points to next DMA2 parameters		      	*/
#define GP1A    0x6c	   /* DMA2 General purpose 		      				*/

/* DMA Channel 3 - Serial Port 1, B channel data */
#define II1B    0x88	   /* Internal DMA3 memory address		      		*/
#define IM1B    0x89	   /* Internal DMA3 memory access modifier	      	*/
#define C1B     0x8a	   /* Contains number of DMA3 transfers remaining   */
#define CP1B    0x8b	   /* Points to next DMA3 parameters		      	*/
#define GP1B    0x8c	   /* DMA3 General purpose		      				*/

/* DMA Channel 4 - Serial Port 2, A channel data 							*/
#define II2A    0x70	   /* Internal DMA4 memory address		      		*/
#define IM2A    0x71	   /* Internal DMA4 memory access modifier	      	*/
#define C2A     0x72	   /* Contains number of DMA4 transfers remaining   */
#define CP2A    0x73	   /* Points to next DMA4 parameters		      	*/
#define GP2A    0x74	   /* DMA4 General purpose		      				*/

/* DMA Channel 5 - Serial Port 2, B channel data */
#define II2B    0x90	   /* Internal DMA5 memory address		      		*/
#define IM2B    0x91	   /* Internal DMA5 memory access modifier	      	*/
#define C2B     0x92	   /* Contains number of DMA5 transfers remaining   */
#define CP2B    0x93	   /* Points to next DMA5 parameters		      	*/
#define GP2B    0x94	   /* DMA5 General purpose		      				*/

/* DMA Channel 6 - Serial Port 3, A channel data */
#define II3A    0x78	   /* Internal DMA6 memory address		      		*/
#define IM3A    0x79	   /* Internal DMA6 memory access modifier	      	*/
#define C3A     0x7a	   /* Contains number of DMA6 transfers remaining   */
#define CP3A    0x7b	   /* Points to next DMA6 parameters		      	*/
#define GP3A    0x7c	   /* DMA6 General purpose		      				*/

/* DMA Channel 7 - Serial Port 3, B channel data */
#define II3B    0x98	   /* Internal DMA7 memory address		      		*/
#define IM3B    0x99	   /* Internal DMA7 memory access modifier	        */
#define C3B     0x9a	   /* Contains number of DMA7 transfers remaining   */
#define CP3B    0x9b	   /* Points to next DMA7 parameters		      	*/
#define GP3B    0x9c	   /* DMA7 General purpose		      				*/

/* DMA Channel 8 - Link Buffer 0 (or SPI Receive) */
#define IILB0   0x30	   /* Internal DMA8 memory address		      		*/
#define IMLB0   0x31	   /* Internal DMA8 memory access modifier	      	*/
#define CLB0    0x32	   /* Contains number of DMA8 transfers remaining   */
#define CPLB0   0x33	   /* Points to next DMA8 parameters		      	*/
#define GPLB0   0x34	   /* DMA8 General purpose		      				*/

/* DMA Channel 8 -  SPI Receive (or Link Buffer 0) - No DMA Chain Pointer reg */
#define IISRX   0x30	   /* Internal DMA8 memory address		      		*/
#define IMSRX   0x31	   /* Internal DMA8 memory access modifier	      	*/
#define CSRX    0x32	   /* Contains number of DMA8 transfers remaining   */
#define GPSRX   0x34	   /* DMA8 General purpose		      				*/

/* DMA Channel 9 - Link Buffer 1 (or SPI Transmit) */
#define IILB1   0x38	   /* Internal DMA9 memory address		      		*/
#define IMLB1   0x39	   /* Internal DMA9 memory access modifier	      	*/
#define CLB1    0x3a	   /* Contains number of DMA9 transfers remaining   */
#define CPLB1   0x3b	   /* Points to next DMA9 parameters		      	*/
#define GPLB1   0x3c	   /* DMA9 General purpose		      				*/

/* DMA Channel 9 -  SPI Transmit (or Link Buffer 1) - No DMA Chain Pointer reg */
#define IISTX    0x38	   /* Internal DMA9 memory address		      		*/
#define IMSTX    0x39	   /* Internal DMA9 memory access modifier	      	*/
#define CSTX     0x3a	   /* Contains number of DMA9 transfers remainnig   */
#define GPSTX    0x3c	   /* DMA9 General purpose */	

/* DMA Channel 10 - External Port FIFO Buffer 0 */
#define IIEP0   0x40	   /* Internal DMA10 memory address					*/
#define IMEP0   0x41	   /* Internal DMA10 memory access modifier	      	*/
#define CEP0    0x42	   /* Contains number of DMA10 transfers remaining  */
#define CPEP0   0x43	   /* Points to next DMA10 parameters		      	*/
#define GPEP0   0x44	   /* DMA10 General purpose			      			*/
#define EIEP0   0x45	   /* External DMA10 address			      		*/
#define EMEP0   0x46	   /* External DMA10 address modifier		      	*/
#define ECEP0   0x47	   /* External DMA10 counter			      		*/

/* DMA Channel 11 - External Port FIFO Buffer 1 */
#define IIEP1   0x48	   /* Internal DMA11 memory address		      		*/
#define IMEP1   0x49	   /* Internal DMA11 memory access modifier	      	*/
#define CEP1    0x4a	   /* Contains number of DMA11 transfers remaining  */
#define CPEP1   0x4b	   /* Points to next DMA11 parameters		      	*/
#define GPEP1   0x4c	   /* DMA11 General purpose			      			*/
#define EIEP1   0x4d	   /* External DMA11 address			      		*/
#define EMEP1   0x4e	   /* External DMA11 address modifier		      	*/
#define ECEP1   0x4f	   /* External DMA counter			      			*/

/* DMA Channel 12 - External Port FIFO Buffer 2 */
#define IIEP2   0x50	   /* Internal DMA12 memory address		      		*/
#define IMEP2   0x51	   /* Internal DMA12 memory access modifier	      	*/
#define CEP2    0x52	   /* Contains number of DMA12 transfers remaining  */
#define CPEP2   0x53	   /* Points to next DMA12 parameters		      	*/
#define GPEP2   0x54	   /* DMA12 General purpose			      			*/
#define EIEP2   0x55	   /* External DMA12 address			      		*/
#define EMEP2   0x56	   /* External DMA12 address modifier		      	*/
#define ECEP2   0x57	   /* External DMA12 counter			      		*/

/* DMA Channel 13 - External Port FIFO Buffer 3 */
#define IIEP3   0x58	   /* Internal DMA13 memory address		      		*/
#define IMEP3   0x59	   /* Internal DMA13 memory access modifier	      	*/
#define CEP3    0x5a	   /* Contains number of DMA13 transfers remaining  */
#define CPEP3   0x5b	   /* Points to next DMA13 parameters		      	*/
#define GPEP3   0x5c	   /* DMA13 General purpose			      			*/
#define EIEP3   0x5d	   /* External DMA13 address			      		*/
#define EMEP3   0x5e	   /* External DMA13 address modifier		     	*/
#define ECEP3   0x5f	   /* External DMA13 counter			      		*/


/*---- DMA Parameter Register Assignments - Old Legacy ADSP-21160 Naming Conventions ---- */
/* NOTE: For backwards compatibility, we can retain the old DMA parameter 
register names used in the ADSP-21160.  However, the naming conventions used for
DMA channels of the ADSP-21160 do not necessarily correspond to the actual DMA channel
priority assigment for the ADSP-21160

Ex) DMA Channel 4 IOP addresses on the ADSP-21160 are now DMA channel 8 on the ADSP-21161
    DMA Channel 5 IOP addresses on the ADSP-21160 are now DMA channel 9 on the ADSP-21161

To clear any confusion, we recommend using the new IOP naming conventions for the 
DMA parameter registers as defined above */

#define II0    0x60	   /* Internal DMA0 memory address		      			*/
#define IM0    0x61	   /* Internal DMA0 memory access modifier	      		*/
#define C0     0x62	   /* Contains number of DMA0 transfers remaining     	*/
#define CP0    0x63	   /* Points to next DMA0 parameters		      		*/
#define GP0    0x64	   /* DMA0 General purpose 		      					*/

#define II1    0x68	   /* Internal DMA1 memory address		      			*/
#define IM1    0x69	   /* Internal DMA1 memory access modifier	      		*/
#define C1     0x6a	   /* Contains number of DMA1 transfers remaining     	*/
#define CP1    0x6b	   /* Points to next DMA1 parameters		      		*/
#define GP1    0x6c	   /* DMA1 General purpose 		      					*/

#define II2    0x70	   	/* Internal DMA2 memory address		      			*/
#define IM2    0x71	   	/* Internal DMA2 memory access modifier	      		*/
#define C2     0x72	   	/* Contains number of DMA2 transfers remaining     	*/
#define CP2    0x73	   	/* Points to next DMA2 parameters		      		*/
#define GP2    0x74	   	/* DMA2 General purpose		      					*/

#define II3    0x78	   /* Internal DMA3 memory address		      			*/
#define IM3    0x79	   /* Internal DMA3 memory access modifier	      		*/
#define C3     0x7a	   /* Contains number of DMA3 transfers remaining     	*/
#define CP3    0x7b	   /* Points to next DMA3 parameters		      		*/
#define GP3    0x7c	   /* DMA3 General purpose 		      					*/

#define II6    0x80	   /* Internal DMA6 memory address		      			*/
#define IM6    0x81	   /* Internal DMA6 memory access modifier	      		*/
#define C6     0x82	   /* Contains number of DMA6 transfers remaining     	*/
#define CP6    0x83	   /* Points to next DMA6 parameters		      		*/
#define GP6    0x84	   /* DMA6 General purpose 		      					*/

#define II7    0x88	   /* Internal DMA7 memory address		      			*/
#define IM7    0x89	   /* Internal DMA7 memory access modifier	      		*/
#define C7     0x8a	   /* Contains number of DMA7 transfers remaining     	*/
#define CP7    0x8b	   /* Points to next DMA7 parameters		      		*/
#define GP7    0x8c	   /* DMA7 General purpose 		      					*/

#define II8    0x90	   /* Internal DMA8 memory address		      			*/
#define IM8    0x91	   /* Internal DMA8 memory access modifier	      		*/
#define C8     0x92	   /* Contains number of DMA8 transfers remaining     	*/
#define CP8    0x93	   /* Points to next DMA8 parameters		      		*/
#define GP8	   0x94	   /* DMA8 General Purpose								*/

#define II9    0x98	   /* Internal DMA9 memory address		      			*/
#define IM9    0x99	   /* Internal DMA9 memory access modifier	      		*/
#define C9     0x9a	   /* Contains number of DMA9 transfers remaining     	*/
#define CP9    0x9b	   /* Points to next DMA9 parameters		      		*/
#define GP9    0x9c	   /* DMA9 General purpose 		      					*/

#define II4    0x30	   /* Internal DMA4 memory address		      			*/
#define IM4    0x31	   /* Internal DMA4 memory access modifier	      		*/
#define C4     0x32	   /* Contains number of DMA4 transfers remaining     	*/
#define CP4    0x33	   /* Points to next DMA4 parameters		      		*/
#define GP4    0x34	   /* DMA4 General purpose 		      					*/

#define II5    0x38	   /* Internal DMA5 memory address		      			*/
#define IM5    0x39	   /* Internal DMA5 memory access modifier	      		*/
#define C5     0x3a	   /* Contains number of DMA5 transfers remaining     	*/
#define CP5    0x3b	   /* Points to next DMA5 parameters		      		*/
#define GP5    0x3c	   /* DMA5 General purpose 		      					*/

#define II10   0x40	   /* Internal DMA10 memory address		      	  		*/
#define IM10   0x41	   /* Internal DMA10 memory access modifier	      		*/
#define C10    0x42	   /* Contains number of DMA10 transfers remaining    	*/
#define CP10   0x43	   /* Points to next DMA10 parameters		      		*/
#define GP10   0x44	   /* DMA10 General purpose			      		  		*/
#define EI10   0x45	   /* External DMA10 address			      	  		*/
#define EM10   0x46	   /* External DMA10 address modifier		      		*/
#define EC10   0x47	   /* External DMA10 counter			      	  		*/

#define II11   0x48	   /* Internal DMA11 memory address		      	  		*/