📄 def21161.h
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#define AVS 0x00000002 /* Bit 1: ALU fltg-pt. overflow */
#define AOS 0x00000004 /* Bit 2: ALU fixed-pt. overflow */
#define AIS 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */
#define MOS 0x00000040 /* Bit 6: Multiplier fixed-pt. overflow */
#define MVS 0x00000080 /* Bit 7: Multiplier fltg-pt. overflow */
#define MUS 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */
#define MIS 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */
/* STKYx register *ONLY* */
#define CB7S 0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow */
#define CB15S 0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow */
#define IIRA 0x00080000 /* Bit 19: Illegal IOP Register Access */
#define U64MA 0x00100000 /* Bit 20: Unaligned 64-bit Memory Access */
#define PCFL 0x00200000 /* Bit 21: PC stack full */
#define PCEM 0x00400000 /* Bit 22: PC stack empty */
#define SSOV 0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT) */
#define SSEM 0x01000000 /* Bit 24: Status stack empty */
#define LSOV 0x02000000 /* Bit 25: Loop stack overflow */
#define LSEM 0x04000000 /* Bit 26: Loop stack empty */
/* IRPTL and IMASK and IMASKP registers */
#define EMUI 0x00000001 /* Bit 0: Offset: 00: Emulator Interrupt */
#define RSTI 0x00000002 /* Bit 1: Offset: 04: Reset */
#define IICDI 0x00000004 /* Bit 2: Offset: 08: Illegal Input Condition Detected */
#define SOVFI 0x00000008 /* Bit 3: Offset: 0c: Stack overflow */
#define TMZHI 0x00000010 /* Bit 4: Offset: 10: Timer = 0 (high priority) */
#define VIRPTI 0x00000020 /* Bit 5: Offset: 14: Vector interrupt */
#define IRQ2I 0x00000040 /* Bit 6: Offset: 18: IRQ2- asserted */
#define IRQ1I 0x00000080 /* Bit 7: Offset: 1c: IRQ1- asserted */
#define IRQ0I 0x00000100 /* Bit 8: Offset: 20: IRQ0- asserted */
#define SP0I 0x00000400 /* Bit 10: Offset: 28: SPORT0 DMA channel */
#define SP1I 0x00000800 /* Bit 11: Offset: 2c: SPORT1 DMA channel */
#define SP2I 0x00001000 /* Bit 12: Offset: 30: SPORT2 DMA channel */
#define SP3I 0x00002000 /* Bit 13: Offset: 34: SPORT3 DMA channel */
#define LPISUMI 0x00004000 /* Bit 14: Offset: na: LPort Interrupt Summary */
#define EP0I 0x00008000 /* Bit 15: Offset: 50: External port channel 0 DMA */
#define EP1I 0x00010000 /* Bit 16: Offset: 54: External port channel 1 DMA */
#define EP2I 0x00020000 /* Bit 17: Offset: 58: External port channel 2 DMA */
#define EP3I 0x00040000 /* Bit 18: Offset: 5c: External port channel 3 DMA */
#define LSRQI 0x00080000 /* Bit 19: Offset: 60: Link service request */
#define CB7I 0x00100000 /* Bit 20: Offset: 64: Circ. buffer 7 overflow */
#define CB15I 0x00200000 /* Bit 21: Offset: 68: Circ. buffer 15 overflow */
#define TMZLI 0x00400000 /* Bit 22: Offset: 6c: Timer = 0 (low priority) */
#define FIXI 0x00800000 /* Bit 23: Offset: 70: Fixed-pt. overflow */
#define FLTOI 0x01000000 /* Bit 24: Offset: 74: fltg-pt. overflow */
#define FLTUI 0x02000000 /* Bit 25: Offset: 78: fltg-pt. underflow */
#define FLTII 0x04000000 /* Bit 26: Offset: 7c: fltg-pt. invalid */
#define SFT0I 0x08000000 /* Bit 27: Offset: 80: user software int 0 */
#define SFT1I 0x10000000 /* Bit 28: Offset: 84: user software int 1 */
#define SFT2I 0x20000000 /* Bit 39: Offset: 88: user software int 2 */
#define SFT3I 0x40000000 /* Bit 30: Offset: 8c: user software int 3 */
/* LIRPTL register */
#define LP0I 0x00000001 /* Bit 0: Offset: 38: Link port channel 0 DMA */
#define LP1I 0x00000002 /* Bit 1: Offset: 3C: Link port channel 1 DMA */
#define SPIRI 0x00000004 /* Bit 2: Offset: 40: SPI Receive DMA */
#define SPITI 0x00000008 /* Bit 3: Offset: 44: SPI Transmit DMA */
#define LP0MSK 0x00010000 /* Bit 16: Link port channel 0 Interrupt Mask */
#define LP1MSK 0x00020000 /* Bit 17: Link port channel 1 Interrupt Mask */
#define SPIRMSK 0x00040000 /* Bit 18: SPI Receive Interrupt Mask */
#define SPITMSK 0x00080000 /* Bit 19: SPI Transmit Interrupt Mask */
#define LP0MSKP 0x01000000 /* Bit 24: Link port channel 0 Interrupt Mask Pointer */
#define LP1MSKP 0x02000000 /* Bit 25: Link port channel 1 Interrupt Mask Pointer */
#define SPIRMSKP 0x04000000 /* Bit 26: SPI Receive Interrupt Mask Pointer */
#define SPITMSKP 0x08000000 /* Bit 27: SPI Transmit Interrupt Mask Pointer */
/* LSRQ register */
#define L0TM 0x00000010 /* Link Port 0 Transmit Mask */
#define L0RM 0x00000020 /* Link Port 0 Receive Mask */
#define L1TM 0x00000040 /* Link Port 1 Transmit Mask */
#define L1RM 0x00000080 /* Link Port 1 Receive Mask */
#define L0TRQ 0x00100000 /* Link Port 0 Transmit Request */
#define L1TRQ 0x00200000 /* Link Port 1 Receive Request */
#define L0RRQ 0x00400000 /* Link Port 0 Transmit Request */
#define L1RRQ 0x00800000 /* Link Port 1 Receive Request */
/*------------------------------------------------------------------------------*/
/* */
/* I/O Processor Register Address Memory Map */
/* */
/*------------------------------------------------------------------------------*/
#define SYSCON 0x00 /* System configuration register */
#define VIRPT 0x01 /* Vector interrupt register */
#define WAIT 0x02 /* External Port Wait register - renamed to EPCON */
#define EPCON 0x02 /* External Port configuration register */
#define SYSTAT 0x03 /* System status register */
/* the upper 32-bits of the 64-bit epbxs are only accessible as 64-bit reference*/
#define EPB0 0x04 /* External port DMA buffer 0 */
#define EPB1 0x06 /* External port DMA buffer 1 */
#define MSGR0 0x08 /* Message register 0 */
#define MSGR1 0x09 /* Message register 1 */
#define MSGR2 0x0a /* Message register 2 */
#define MSGR3 0x0b /* Message register 3 */
#define MSGR4 0x0c /* Message register 4 */
#define MSGR5 0x0d /* Message register 5 */
#define MSGR6 0x0e /* Message register 6 */
#define MSGR7 0x0f /* Message register 7 */
/* IOP shadow registers of the core control regs */
#define PC_SHDW 0x10 /* PC IOP shadow register (PC[23-0]) */
#define MODE2_SHDW 0x11 /* Mode2 IOP shadow register (MODE2[31-25]) */
#define EPB2 0x14 /* External port DMA buffer 2 */
#define EPB3 0x16 /* External port DMA buffer 3 */
#define BMAX 0x18 /* Bus time-out maximum */
#define BCNT 0x19 /* Bus time-out counter */
#define DMAC10 0x1c /* EP DMA10 control register */
#define DMAC11 0x1d /* EP DMA11 control register */
#define DMAC12 0x1e /* EP DMA12 control register */
#define DMAC13 0x1f /* EP DMA13 control register */
#define DMASTAT 0x37 /* DMA channel status register */
/* SPI Registers IOP Register Addresses*/
#define SPICTL 0xb4 /* Serial peripheral-compatible interface control register */
#define SPISTAT 0xb5 /* Serial periipheral-compatible interface status register */
#define SPIRX 0xb7 /* SPI receive data buffer */
#define SPITX 0xb6 /* SPI transmit data buffer */
/* IOFLAG Register Address */
#define IOFLAG 0x1b /* Address of programmable I/O flags 4-11 */
/* IOP registers for SDRAM controller. */
#define SDCTL 0xb8 /* SDRAM control reg. */
#define SDRDIV 0xb9 /* Refresh counter div reg. */
/* Link Port Registers */
#define LBUF0 0xc0 /* Link buffer 0 */
#define LBUF1 0xc2 /* Link buffer 1 */
#define LCTL 0xcc /* Link buffer control */
#define LSRQ 0xd0 /* Link service request and mask registers */
/* SPORT0 */
#define SPCTL0 0x1c0 /* SPORT0 serial port control register */
#define TX0A 0x1c1 /* SPORT0 serial port control register */
#define TX0B 0x1c2 /* SPORT0 transmit secondary B channel data buffer */
#define RX0A 0x1c3 /* SPORT0 receive primary A channel data buffer */
#define RX0B 0x1c4 /* SPORT0 receive secondary B channel data buffer */
#define DIV0 0x1c5 /* SPORT0 divisor for transmit/receive SLCK0 and FS0 */
#define CNT0 0x1c6 /* SPORT0 count register */
/* SPORT2 */
#define SPCTL2 0x1d0 /* SPORT2 serial port control register */
#define TX2A 0x1d1 /* SPORT2 serial port control register */
#define TX2B 0x1d2 /* SPORT2 transmit secondary B channel data buffer */
#define RX2A 0x1d3 /* SPORT2 receive primary A channel data buffer */
#define RX2B 0x1d4 /* SPORT2 receive secondary B channel data buffer */
#define DIV2 0x1d5 /* SPORT2 divisor for transmit/receive SLCK2 and FS2 */
#define CNT2 0x1d6 /* SPORT2 count register */
/* SPORT1 */
#define SPCTL1 0x1e0 /* SPORT1 serial port control register */
#define TX1A 0x1e1 /* SPORT1 serial port control register */
#define TX1B 0x1e2 /* SPORT1 transmit secondary B channel data buffer */
#define RX1A 0x1e3 /* SPORT1 receive primary A channel data buffer */
#define RX1B 0x1e4 /* SPORT1 receive secondary B channel data buffer */
#define DIV1 0x1e5 /* SPORT1 divisor for transmit/receive SLCK1 and FS1 */
#define CNT1 0x1e6 /* SPORT1 count register */
/* SPORT3 */
#define SPCTL3 0x1f0 /* SPORT3 serial port control register */
#define TX3A 0x1f1 /* SPORT3 serial port control register */
#define TX3B 0x1f2 /* SPORT3 transmit secondary B channel data buffer */
#define RX3A 0x1f3 /* SPORT3 receive primary A channel data buffer */
#define RX3B 0x1f4 /* SPORT3 receive secondary B channel data buffer */
#define DIV3 0x1f5 /* SPORT3 divisor for transmit/receive SLCK3 and FS3 */
#define CNT3 0x1f6 /* SPORT3 count register */
/* SPORT0 - MCM Receive (Works in pair with SPORT2) */
#define MR0CS0 0x1c7 /* SPORT0 multichannel rx select, channels 31 - 0 */
#define MR0CCS0 0x1c8 /* SPORT0 multichannel rx compand select, channels 31 - 0 */
#define MR0CS1 0x1c9 /* SPORT0 multichannel rx select, channels 63 - 32 */
#define MR0CCS1 0x1ca /* SPORT0 multichannel rx compand select, channels 63 - 32 */
#define MR0CS2 0x1cb /* SPORT0 multichannel rx select, channels 95 - 64 */
#define MR0CCS2 0x1cc /* SPORT0 multichannel rx compand select, channels 95 - 64 */
#define MR0CS3 0x1cd /* SPORT0 multichannel rx select, channels 127 - 96 */
#define MR0CCS3 0x1ce /* SPORT0 multichannel rx compand select, channels 127 - 96 */
/* SPORT2 - MCM Transmit (Works in pair with SPORT0) */
#define MT2CS0 0x1d7 /* SPORT2 multichannel tx select, channels 31 - 0 */
#define MT2CCS0 0x1d8 /* SPORT2 multichannel tx compand select, channels 31 - 0 */
#define MT2CS1 0x1d9 /* SPORT2 multichannel tx select, channels 63 - 32 */
#define MT2CCS1 0x1da /* SPORT2 multichannel tx compand select, channels 63 - 32 */
#define MT2CS2 0x1db /* SPORT2 multichannel tx select, channels 95 - 64 */
#define MT2CCS2 0x1dc /* SPORT2 multichannel tx compand select, channels 95 - 64 */
#define MT2CS3 0x1dd /* SPORT2 multichannel tx select, channels 127 - 96 */
#define MT2CCS3 0x1de /* SPORT2 multichannel tx compand select, channels 127 - 96 */
#define SP02MCTL 0x1df /* SPORTs 0 & 2 Multichannel Control Register */
/* SPORT1 - MCM Receive (Works in pair with SPORT3) */
#define MR1CS0 0x1e7 /* SPORT1 multichannel rx select, channels 31 - 0 */
#define MR1CCS0 0x1e8 /* SPORT1 multichannel rx compand select, channels 31 - 0 */
#define MR1CS1 0x1e9 /* SPORT1 multichannel rx select, channels 63 - 32 */
#define MR1CCS1 0x1ea /* SPORT1 multichannel rx compand select, channels 63 - 32 */
#define MR1CS2 0x1eb /* SPORT1 multichannel rx select, channels 95 - 64 */
#define MR1CCS2 0x1ec /* SPORT1 multichannel rx compand select, channels 95 - 64 */
#define MR1CS3 0x1ed /* SPORT1 multichannel rx select, channels 127 - 96 */
#define MR1CCS3 0x1ee /* SPORT1 multichannel rx compand select, channels 127 - 96 */
/* SPORT3 - MCM Transmit (Works in pair with SPORT1) */
#define MT3CS0 0x1f7 /* SPORT3 multichannel tx select, channels 31 - 0 */
#define MT3CCS0 0x1f8 /* SPORT3 multichannel tx compand select, channels 31 - 0 */
#define MT3CS1 0x1f9 /* SPORT3 multichannel tx select, channels 63 - 32 */
#define MT3CCS1 0x1fa /* SPORT3 multichannel tx compand select, channels 63 - 32 */
#define MT3CS2 0x1fb /* SPORT3 multichannel tx select, channels 95 - 64 */
#define MT3CCS2 0x1fc /* SPORT3 multichannel tx compand select, channels 95 - 64 */
#define MT3CS3 0x1fd /* SPORT3 multichannel tx select, channels 127 - 96 */
#define MT3CCS3 0x1fe /* SPORT3 multichannel tx compand select, channels 127 - 96 */
#define SP13MCTL 0x1ff /* SPORTs 1 & 3 Multichannel Control Register */
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