📄 def21161.h
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/************************************************************************
*
* def21161.h
*
* (c) Copyright 2001 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
/* ----------------------------------------------------------------------------
def21161.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21161
Last updated 5/14/01
This include file contains a list of macro "defines" to enable the programmer
to use symbolic names for the following ADSP-21161 facilities:
- instruction condition codes
- system register bit definitions
- IOP register address memory map
- *most* IOP control/status register bit definitions
Changes from def21160 include new I/O flags, SDRAM and SPI interfaces, changes to SPORT,
Link Port, and DMA.
* 2/12/01 J.T.
- fixed WAIT Register Bitfields for ROM Boot waitstates and waitmode
- removed IMGR bit 29 in SYSCON, since no mesh processing on 21161
- removed L1DMA2D and L2DMA2D bits in LCTL since no 2-D DMA
- removed 2DDMA references to older SPORT/Link DMA parameter register naming conventions
- moved DMASTAT reg out of DMA parameters section to general IOP reg section
- moved Link Port and SPORT Registers to general IOP section
- added defs under IOP register bitfields section for MODE2_SHDW (0x11)
- fixed comments for LDCPR bit in SYSCON to indicate DMA chs 8 & 9
- rearranged SYSTAT bitfield definitions to correct order
- added LSRQ, DMAC10, DMAC11, DMAC12, DMAC13, DMASTAT, bitfield definitions
- fixed SPICTL bitfield hex assignments (per G.L.) for bits 24 to 31
- added bitfield descriptions for IOFLAG, SPICTL, SPISTAT and LCTL IOP registers
- removed LARB0, LARB1 bits and added A0LB, L1LB bits in LCTL as shown in
21160/21161 HW reference manuals and for 2106x code compatibility
- added SPCTL0/1/2/3 register bitfield definitions for I2S, DSP serial
and multichannel modes
- fixed which STKYx/y bits pertain only to STKYx register
- added G.L.'s alternate SPI DMA parameter register naming conventions
- added IOP register name descriptions in comments field for all
SPI and SPORT registers
- added SP02MCTL and SP13MCTL bitfield descriptions
- added additional SPORT bitfied definitions from G.L.
* 2/13/01 - JT
- changed RBWx bits in WAIT to RBWMx to reflect 21065L compatibility
- changed WAIT register bits for def21160.H compatibility
- added generic WAIT register bits consistant with HW ref manual
- added new WAIT register bitfields for all waitstates and waitmodes combos
- fixed comment fields for SPORTx multichannel select registers
- more detailed comment fields for SDCTL register
* 2/15/01 - JT
- fixed 'tRCD' comment under SDRAM bitfield description for tRAS
* 2/21/01 - TK
- fixed definition of EBxAM entries
- fixed definition of EBxWSx entries
* 2/22/01 - JT
- added alternate LAB0 and LAB1 definitions in LCTL
* 2/23/01 - JT
- renamed SDCTL bitfield SDCKRx2 to SDCKR_DIV2
* 03/05/01 - TK
- fixed example
* 03/09/01 - JT
- fixed SDTRCD comments in SDCTL from "CAS-to-RAS" to "RAS-to-CAS" delay
* 04/02/01 - JT
- renamed (alternale link port) SPI DMA count definitions to CSRX and CSTX
* 04/03/01 - GL
- fixed boot wait state definations so that RBWS0 and RBWS1 refer to the actual bit positions and
RBWS0:RBWS7 are changed to RBWST0:RBWST7 so that they don't confict with the bit position definitions
* 05/14/01 - JT
- In WAIT register, changed "RBWM" bits to "RMAM" to confirm with defs for banks 0 to 3
* 07/04/01 - TK
- fixed SENDN bit entry for SPCTLx registers
Here are some example uses:
bit set mode1 BR0|IRPTEN|ALUSAT;
ustat1=BSO|HPM01|HMSWF;
DM(SYSCON)=ustat1;
----------------------------------------------------------------------------- */
#ifndef __DEF21161_H_
#define __DEF21161_H_
/*----------------------------------------------------------------------------*/
/* System Register bit definitions */
/*----------------------------------------------------------------------------*/
/* MODE1 and MMASK registers */
#define BR8 0x00000001 /* Bit 0: Bit-reverse for I8 */
#define BR0 0x00000002 /* Bit 1: Bit-reverse for I0 (uses DMS0- only ) */
#define SRCU 0x00000004 /* Bit 2: Alt. register select for comp. units */
#define SRD1H 0x00000008 /* Bit 3: DAG1 alt. register select (7-4) */
#define SRD1L 0x00000010 /* Bit 4: DAG1 alt. register select (3-0) */
#define SRD2H 0x00000020 /* Bit 5: DAG2 alt. register select (15-12) */
#define SRD2L 0x00000040 /* Bit 6: DAG2 alt. register select (11-8) */
#define SRRFH 0x00000080 /* Bit 7: Register file alt. select for R(15-8) */
#define SRRFL 0x00000400 /* Bit 10: Register file alt. select for R(7-0) */
#define NESTM 0x00000800 /* Bit 11: Interrupt nesting enable */
#define IRPTEN 0x00001000 /* Bit 12: Global interrupt enable */
#define ALUSAT 0x00002000 /* Bit 13: Enable ALU fixed-pt. saturation */
#define SSE 0x00004000 /* Bit 14: Enable short word sign extension */
#define TRUNCATE 0x00008000 /* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest */
#define RND32 0x00010000 /* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd */
#define CSEL 0x00060000 /* Bit 17-18: CSelect: Bus Mastership */
#define PEYEN 0x00200000 /* Bit 21: Processing Element Y enable */
#define SIMD 0x00200000 /* Bit 21: Enable SIMD Mode */
#define BDCST9 0x00400000 /* Bit 22: Load Broadcast for I9 */
#define BDCST1 0x00800000 /* Bit 23: Load Broadcast for I1 */
#define CBUFEN 0x01000000 /* Bit 23: Circular Buffer Enable */
/* MODE2 register */
#define IRQ0E 0x00000001 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */
#define IRQ1E 0x00000002 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */
#define IRQ2E 0x00000004 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */
#define CADIS 0x00000010 /* Bit 4: Cache disable */
#define TIMEN 0x00000020 /* Bit 5: Timer enable */
#define BUSLK 0x00000040 /* Bit 6: External bus lock */
#define FLG0O 0x00008000 /* Bit 15: FLAG0 1=output 0=input */
#define FLG1O 0x00010000 /* Bit 16: FLAG1 1=output 0=input */
#define FLG2O 0x00020000 /* Bit 17: FLAG2 1=output 0=input */
#define FLG3O 0x00040000 /* Bit 18: FLAG3 1=output 0=input */
#define CAFRZ 0x00080000 /* Bit 19: Cache freeze */
#define IIRAE 0x00100000 /* Bit 20: Illegal IOP Register Access Enable */
#define U64MAE 0x00200000 /* Bit 21: Unaligned 64-bit Memory Access Enable */
/* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 0b01001
bits 29-28 are silicon revision[1:0], read only, value: 0
These bits (only) are routed to Mode2 Shadow register (IOP register 0x11)
*/
/* FLAGS register */
#define FLG0 0x00000001 /* Bit 0: FLAG0 value */
#define FLG1 0x00000002 /* Bit 1: FLAG1 value */
#define FLG2 0x00000004 /* Bit 2: FLAG2 value */
#define FLG3 0x00000008 /* Bit 3: FLAG3 value */
/* ASTATx and ASTATy registers */
#ifdef SUPPORT_DEPRECATED_USAGE
/* Several of these (AV, AC, MV, SV, SZ) are assembler-reserved keywords,
so this style is now deprecated. If these are defined, the assembler-
reserved keywords are still available in lowercase, e.g.,
IF sz JUMP LABEL1.
*/
# define AZ 0x00000001 /* Bit 0: ALU result zero or fltg-pt. underflow */
# define AV 0x00000002 /* Bit 1: ALU overflow */
# define AN 0x00000004 /* Bit 2: ALU result negative */
# define AC 0x00000008 /* Bit 3: ALU fixed-pt. carry */
# define AS 0x00000010 /* Bit 4: ALU X input sign (ABS and MANT ops) */
# define AI 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */
# define MN 0x00000040 /* Bit 6: Multiplier result negative */
# define MV 0x00000080 /* Bit 7: Multiplier overflow */
# define MU 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */
# define MI 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */
# define AF 0x00000400 /* Bit 10: ALU fltg-pt. operation */
# define SV 0x00000800 /* Bit 11: Shifter overflow */
# define SZ 0x00001000 /* Bit 12: Shifter result zero */
# define SS 0x00002000 /* Bit 13: Shifter input sign */
# define BTF 0x00040000 /* Bit 18: Bit test flag for system registers */
# define CACC0 0x01000000 /* Bit 24: Compare Accumulation Bit 0 */
# define CACC1 0x02000000 /* Bit 25: Compare Accumulation Bit 1 */
# define CACC2 0x04000000 /* Bit 26: Compare Accumulation Bit 2 */
# define CACC3 0x08000000 /* Bit 27: Compare Accumulation Bit 3 */
# define CACC4 0x10000000 /* Bit 28: Compare Accumulation Bit 4 */
# define CACC5 0x20000000 /* Bit 29: Compare Accumulation Bit 5 */
# define CACC6 0x40000000 /* Bit 30: Compare Accumulation Bit 6 */
# define CACC7 0x80000000 /* Bit 31: Compare Accumulation Bit 7 */
#endif
#define ASTAT_AZ 0x00000001 /* Bit 0: ALU result zero or fltg-pt. u'flow*/
#define ASTAT_AV 0x00000002 /* Bit 1: ALU overflow */
#define ASTAT_AN 0x00000004 /* Bit 2: ALU result negative */
#define ASTAT_AC 0x00000008 /* Bit 3: ALU fixed-pt. carry */
#define ASTAT_AS 0x00000010 /* Bit 4: ALU X input sign(ABS and MANT ops)*/
#define ASTAT_AI 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */
#define ASTAT_MN 0x00000040 /* Bit 6: Multiplier result negative */
#define ASTAT_MV 0x00000080 /* Bit 7: Multiplier overflow */
#define ASTAT_MU 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */
#define ASTAT_MI 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid op. */
#define ASTAT_AF 0x00000400 /* Bit 10: ALU fltg-pt. operation */
#define ASTAT_SV 0x00000800 /* Bit 11: Shifter overflow */
#define ASTAT_SZ 0x00001000 /* Bit 12: Shifter result zero */
#define ASTAT_SS 0x00002000 /* Bit 13: Shifter input sign */
#define ASTAT_BTF 0x00040000 /* Bit 18: Bit test flag for system registers*/
#define ASTAT_CACC0 0x01000000 /* Bit 24: Compare Accumulation Bit 0 */
#define ASTAT_CACC1 0x02000000 /* Bit 25: Compare Accumulation Bit 1 */
#define ASTAT_CACC2 0x04000000 /* Bit 26: Compare Accumulation Bit 2 */
#define ASTAT_CACC3 0x08000000 /* Bit 27: Compare Accumulation Bit 3 */
#define ASTAT_CACC4 0x10000000 /* Bit 28: Compare Accumulation Bit 4 */
#define ASTAT_CACC5 0x20000000 /* Bit 29: Compare Accumulation Bit 5 */
#define ASTAT_CACC6 0x40000000 /* Bit 30: Compare Accumulation Bit 6 */
#define ASTAT_CACC7 0x80000000 /* Bit 31: Compare Accumulation Bit 7 */
/* STKYx and STKYy registers */
/* bits 0 to 9 in both STKYx and STKYY, bits 17 to 26 in STKYx only */
#define AUS 0x00000001 /* Bit 0: ALU fltg-pt. underflow */
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