dma_burst.asm

2005 Center for Biological & Computational Learning at MIT and MIT All rights reserved. Permissio

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#include <def21160.h>

#define N 16		// number of 32-bit words to transfer

.GLOBAL		_main;

.section/dm seg_sbsram;
.var rx_buffer[N]; 

.section/dm seg_dmda;
.var tx_buffer[N] =			0x00000000, 0x11111111, 0x22222222, 0x33333333, 
							0x44444444, 0x55555555, 0x66666666, 0x77777777, 
							0x88888888, 0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 
							0xcccccccc, 0xdddddddd, 0xeeeeeeee, 0xffffffff;

.section/pm seg_pmco;
start:
_main:

		// enable external port 0 DMA and global interupts
		bit set imask EP0I;			
		bit set MODE1 IRPTEN;		

		// set MSIZE 1100
		ustat1 = dm(SYSCON);		
		bit set ustat1 0x0000C000; 	
		dm(SYSCON) = ustat1;		

		// set the External Port 0 waitstates to 1 
		ustat1 = dm(WAIT);				
		bit set ustat1 0x00000080; 		
		bit clr ustat1 0x00000300; 	
		dm(WAIT) = ustat1;		

	Setup_Send_Internal_Data_DMA:
		r0=0;		
		dm(DMAC10)=r0;  // Clear DMA Control Register
	
	    r0=tx_buffer; 	
		dm(II10)=r0; 	// load IIx register with int. mem. source
	
		r0=1;     	
		dm(IM10)=r0; 	// load internal modify value  
	  
	    r0=N;	
		dm(C10)=r0;  	// load internal count value
	
	    r0=rx_buffer;   	
		dm(EI10)=r0; 	// load EIx register with destination in ext. mem.
	
	    r0=1;      	
		dm(EM10)=r0; 	// load external modify value
	
	    r0=N;	
		dm(EC10)=r0; 	// load external count
	
		r0=0x00000405; 	
		dm(DMAC10)=r0;  // dma enable, int>ext, master mode		                
		
		idle;

wait0: jump wait0;

_main.end: