pcatio.c

来自「EFI BIOS是Intel提出的下一代的BIOS标准。这里上传的Edk源代码是」· C语言 代码 · 共 734 行 · 第 1/2 页

      IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
      Register |= 0x02;
      IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);

      //
      // Recurse on the Secondary Bus Number
      //
      ScanPciBus(
        IoDev,
        PciBridgeHeader->Bridge.SecondaryBus, PciBridgeHeader->Bridge.SecondaryBus, 
        0, PCI_MAX_DEVICE, 
        0, PCI_MAX_FUNC, 
        CheckForRom, Context
        );
    }
  } else {

    //
    // Check if an Option ROM Register is present and save the Option ROM Window Register
    //
    RomBar = 0xffffffff;
    IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
    IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);

    RomBarSize = (~(RomBar & 0xfffff800)) + 1;

    //
    // Make sure the size of the ROM is between 0 and 16 MB
    //
    if (RomBarSize > 0 && RomBarSize <= 0x01000000) {

      //
      // Program Option ROM Window Register to the PCI Root Bridge Window and Enable the Option ROM Window
      //
      RomBar = (Context->PpbMemoryWindow & 0xffff) << 16;
      RomBar = ((RomBar - 1) & (~(RomBarSize - 1))) + RomBarSize;
      if (RomBar < (Context->PpbMemoryWindow & 0xffff0000)) {
        MaxRomSize = (Context->PpbMemoryWindow & 0xffff0000) - RomBar;
        RomBar = RomBar + 1;
        IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
        IoDev->Pci.Read  (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
        RomBar = RomBar - 1;

        //
        // Enable the Memory decode for the PCI Device
        //
        IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
        Register |= 0x02;
        IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);

        //
        // Follow the chain of images to determine the size of the Option ROM present
        // Keep going until the last image is found by looking at the Indicator field
        // or the size of an image is 0, or the size of all the images is bigger than the
        // size of the window programmed into the PPB.
        //
        RomBarSize = 0;
        do {

          LastImage = TRUE;

          EfiZeroMem (&EfiRomHeader, sizeof(EfiRomHeader));
          IoDev->Mem.Read (
            IoDev, 
            EfiPciWidthUint8, 
            RomBar + RomBarSize, 
            sizeof(EfiRomHeader),
            &EfiRomHeader
            );

          Pcir.ImageLength = 0;

          if (EfiRomHeader.Signature == 0xaa55) {

            EfiZeroMem (&Pcir, sizeof(Pcir));
            IoDev->Mem.Read (
              IoDev, 
              EfiPciWidthUint8, 
              RomBar + RomBarSize + EfiRomHeader.PcirOffset, 
              sizeof(Pcir),
              &Pcir
              );

            if ((Pcir.Indicator & 0x80) == 0x00) {
              LastImage = FALSE;
            }

            RomBarSize += Pcir.ImageLength * 512;
          }
        } while (!LastImage && RomBarSize < MaxRomSize && Pcir.ImageLength !=0);

        if (RomBarSize > 0) {

          //
          // Allocate a memory buffer for the Option ROM contents.
          //
          Status = gBS->AllocatePages(
                          AllocateAnyPages,
                          EfiBootServicesData,
                          EFI_SIZE_TO_PAGES(RomBarSize),
                          &RomBuffer
                          );

          if (!EFI_ERROR (Status)) {

            //
            // Copy the contents of the Option ROM to the memory buffer
            //
            IoDev->Mem.Read (IoDev, EfiPciWidthUint32, RomBar, RomBarSize / sizeof(UINT32), (VOID *)(UINTN)RomBuffer);

            Status = gBS->AllocatePool(
                            EfiBootServicesData,
                            ((UINT32)mPciOptionRomTable.PciOptionRomCount + 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR),
                            &TempPciOptionRomDescriptors
                            );
            if (mPciOptionRomTable.PciOptionRomCount > 0) {
              EfiCopyMem(
                TempPciOptionRomDescriptors, 
                mPciOptionRomTable.PciOptionRomDescriptors, 
                (UINT32)mPciOptionRomTable.PciOptionRomCount * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR)
                );

              gBS->FreePool(mPciOptionRomTable.PciOptionRomDescriptors);
            }

            mPciOptionRomTable.PciOptionRomDescriptors = TempPciOptionRomDescriptors; 

            TempPciOptionRomDescriptors = &(mPciOptionRomTable.PciOptionRomDescriptors[(UINT32)mPciOptionRomTable.PciOptionRomCount]);

            TempPciOptionRomDescriptors->RomAddress              = RomBuffer;
            TempPciOptionRomDescriptors->MemoryType              = EfiBootServicesData;
            TempPciOptionRomDescriptors->RomLength               = RomBarSize;
            TempPciOptionRomDescriptors->Seg                     = (UINT32)IoDev->SegmentNumber;
            TempPciOptionRomDescriptors->Bus                     = (UINT8)Bus;
            TempPciOptionRomDescriptors->Dev                     = (UINT8)Device;
            TempPciOptionRomDescriptors->Func                    = (UINT8)Func;
            TempPciOptionRomDescriptors->ExecutedLegacyBiosImage = TRUE;
            TempPciOptionRomDescriptors->DontLoadEfiRom          = FALSE;

            mPciOptionRomTable.PciOptionRomCount++;
          }
        }

        //
        // Disable the Memory decode for the PCI-PCI Bridge
        //
        IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
        Register &= (~0x02);
        IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
      }
    }
  }

  //
  // Restore the PCI Configuration Header 
  //
  IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);
}

static
VOID
SaveCommandRegister (
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,
  UINT16                           MinBus,
  UINT16                           MaxBus,
  UINT16                           MinDevice,
  UINT16                           MaxDevice,
  UINT16                           MinFunc,
  UINT16                           MaxFunc,
  UINT16                           Bus,
  UINT16                           Device,
  UINT16                           Func,
  IN VOID                          *VoidContext
  )

{
  PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT  *Context;
  UINT64  Address;
  UINTN   Index;
  UINT16  Command;

  Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;

  Address = EFI_PCI_ADDRESS (Bus, Device, Func, 4);

  Index = (Bus - MinBus) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1) + Device * (PCI_MAX_FUNC+1) + Func;

  IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address, 1, &Context->CommandRegisterBuffer[Index]);

  //
  // Clear the memory enable bit
  //
  Command = Context->CommandRegisterBuffer[Index] & (~0x02);

  IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Command);
}

static
VOID
RestoreCommandRegister (
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,
  UINT16                           MinBus,
  UINT16                           MaxBus,
  UINT16                           MinDevice,
  UINT16                           MaxDevice,
  UINT16                           MinFunc,
  UINT16                           MaxFunc,
  UINT16                           Bus,
  UINT16                           Device,
  UINT16                           Func,
  IN VOID                          *VoidContext
  )

{
  PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT  *Context;
  UINT64                                     Address;
  UINTN                                      Index;

  Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;

  Address = EFI_PCI_ADDRESS (Bus, Device, Func, 4);

  Index = (Bus - MinBus) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1) + Device * (PCI_MAX_FUNC+1) + Func;

  IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Context->CommandRegisterBuffer[Index]);
}

EFI_STATUS
ScanPciRootBridgeForRoms(
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev
  )
  
{
  EFI_STATUS                                 Status;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR          *Descriptors; 
  UINT16                                     MinBus;
  UINT16                                     MaxBus;
  UINT64                                     RootWindowBase;
  UINT64                                     RootWindowLimit;
  PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT  Context;

  if (mPciOptionRomTableInstalled == FALSE) {
    gBS->InstallConfigurationTable(&gEfiPciOptionRomTableGuid, &mPciOptionRomTable);
    mPciOptionRomTableInstalled = TRUE;
  }

  Status = IoDev->Configuration(IoDev, &Descriptors);
  if (EFI_ERROR (Status) || Descriptors == NULL) {
    return EFI_NOT_FOUND;
  }

  MinBus = 0xffff;
  MaxBus = 0xffff;
  RootWindowBase  = 0;
  RootWindowLimit = 0;
  while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {
    //
    // Find bus range
    //
    if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
      MinBus = (UINT16)Descriptors->AddrRangeMin;
      MaxBus = (UINT16)Descriptors->AddrRangeMax;
    }
    //
    // Find memory descriptors that are not prefetchable
    //
    if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM && Descriptors->SpecificFlag == 0) {
      //
      // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices
      //
      if (Descriptors->AddrRangeMax < 0x100000000) {
        //
        // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB
        //
        if ((Descriptors->AddrRangeMax - Descriptors->AddrRangeMin) > (RootWindowLimit - RootWindowBase)) {
          RootWindowBase  = Descriptors->AddrRangeMin;
          RootWindowLimit = Descriptors->AddrRangeMax;
        }
      }
    }
    Descriptors ++;
  }

  //
  // Make sure a bus range was found
  //
  if (MinBus == 0xffff || MaxBus == 0xffff) {
    return EFI_NOT_FOUND;
  }

  //
  // Make sure a non-prefetchable memory region was found
  //
  if (RootWindowBase == 0 && RootWindowLimit == 0) {
    return EFI_NOT_FOUND;
  }

  //
  // Round the Base and Limit values to 1 MB boudaries
  //
  RootWindowBase  = ((RootWindowBase - 1) & 0xfff00000) + 0x00100000;
  RootWindowLimit = ((RootWindowLimit + 1) & 0xfff00000) - 1;

  //
  // Make sure that the size of the rounded window is greater than zero
  //
  if (RootWindowLimit <= RootWindowBase) {
    return EFI_NOT_FOUND;
  }

  //
  // Allocate buffer to save the Command register from all the PCI devices
  //
  Context.CommandRegisterBuffer = NULL;
  Status = gBS->AllocatePool(
                  EfiBootServicesData,
                  sizeof(UINT16) * (MaxBus - MinBus + 1) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1),
                  &Context.CommandRegisterBuffer
                  );

  if (EFI_ERROR (Status)) {
    return Status;
  }

  Context.PpbMemoryWindow   = (((UINT32)RootWindowBase) >> 16) | ((UINT32)RootWindowLimit & 0xffff0000);

  //
  // Save the Command register from all the PCI devices, and disable the I/O, Mem, and BusMaster bits
  //
  ScanPciBus(
    IoDev,
    MinBus, MaxBus, 
    0, PCI_MAX_DEVICE, 
    0, PCI_MAX_FUNC, 
    SaveCommandRegister, &Context
    );

  //
  // Recursively scan all the busses for PCI Option ROMs
  //
  ScanPciBus(
    IoDev,
    MinBus, MinBus, 
    0, PCI_MAX_DEVICE, 
    0, PCI_MAX_FUNC, 
    CheckForRom, &Context
    );

  //
  // Restore the Command register in all the PCI devices
  //
  ScanPciBus(
    IoDev,
    MinBus, MaxBus, 
    0, PCI_MAX_DEVICE, 
    0, PCI_MAX_FUNC, 
    RestoreCommandRegister, &Context
    );

  //
  // Free the buffer used to save all the Command register values
  //
  gBS->FreePool(Context.CommandRegisterBuffer);

  return EFI_SUCCESS;
}