idedata.h

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#define SINGLE_WORD_DMA_TRANSFER_MODE                   (0x10)
#define MULTI_WORD_DMA_TRANSFER_MODE                    (0x20)
#define TRANSFER_MODE_MASK                              (0x07)  // 3 LSBs

//
// Drive 0 - Head 0
//
#define DEFAULT_DRIVE (0x00)
#define DEFAULT_CMD   (0xa0)
//
// default content of device control register, disable INT
//
#define DEFAULT_CTL                 (0x0a)
#define DEFAULT_IDE_BM_IO_BASE_ADR  (0xffa0)

//
// ATAPI6 related data structure definition
//

//
// The maximum sectors count in 28 bit addressing mode
//
#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff

//
// Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
//

//
// ATAPI Command
//
#define ATAPI_SOFT_RESET_CMD      0x08
#define ATAPI_PACKET_CMD          0xA0
#define PACKET_CMD                0xA0
#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
#define ATAPI_SERVICE_CMD         0xA2

//
// ATAPI Packet Command
//
#pragma pack(1)

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1;
  UINT8 reserved_2;
  UINT8 reserved_3;
  UINT8 reserved_4;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 reserved_7;
  UINT8 reserved_8;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} TEST_UNIT_READY_CMD;

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1 : 4;
  UINT8 lun : 4;
  UINT8 page_code;
  UINT8 reserved_3;
  UINT8 allocation_length;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 reserved_7;
  UINT8 reserved_8;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} INQUIRY_CMD;

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1 : 4;
  UINT8 lun : 4;
  UINT8 reserved_2;
  UINT8 reserved_3;
  UINT8 allocation_length;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 reserved_7;
  UINT8 reserved_8;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} REQUEST_SENSE_CMD;

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1 : 4;
  UINT8 lun : 4;
  UINT8 page_code : 4;
  UINT8 page_control : 4;
  UINT8 reserved_3;
  UINT8 reserved_4;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 parameter_list_length_hi;
  UINT8 parameter_list_length_lo;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} MODE_SENSE_CMD;

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1 : 5;
  UINT8 lun : 3;
  UINT8 Lba0;
  UINT8 Lba1;
  UINT8 Lba2;
  UINT8 Lba3;
  UINT8 reserved_6;
  UINT8 TranLen0;
  UINT8 TranLen1;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} READ10_CMD;

typedef struct {
  UINT8 opcode;
  UINT8 reserved_1;
  UINT8 reserved_2;
  UINT8 reserved_3;
  UINT8 reserved_4;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 allocation_length_hi;
  UINT8 allocation_length_lo;
  UINT8 reserved_9;
  UINT8 reserved_10;
  UINT8 reserved_11;
} READ_FORMAT_CAP_CMD;

typedef union {
  UINT16              Data16[6];
  TEST_UNIT_READY_CMD TestUnitReady;
  READ10_CMD          Read10;
  REQUEST_SENSE_CMD   RequestSence;
  INQUIRY_CMD         Inquiry;
  MODE_SENSE_CMD      ModeSense;
  READ_FORMAT_CAP_CMD ReadFormatCapacity;
} ATAPI_PACKET_COMMAND;

typedef struct {
  UINT32  RegionBaseAddr;
  UINT16  ByteCount;
  UINT16  EndOfTable;
} IDE_DMA_PRD;

#define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
#define MAX_DMA_COMMAND_SECTORS     0x100

#pragma pack()

//
// Packet Command Code
//
#define TEST_UNIT_READY             0x00
#define REZERO                      0x01
#define REQUEST_SENSE               0x03
#define FORMAT_UNIT                 0x04
#define REASSIGN_BLOCKS             0x07
#define INQUIRY                     0x12
#define START_STOP_UNIT             0x1B
#define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
#define READ_FORMAT_CAPACITY        0x23
#define OLD_FORMAT_UNIT             0x24
#define READ_CAPACITY               0x25
#define READ_10                     0x28
#define WRITE_10                    0x2A
#define SEEK                        0x2B
#define SEND_DIAGNOSTICS            0x3D
#define WRITE_VERIFY                0x2E
#define VERIFY                      0x2F
#define READ_DEFECT_DATA            0x37
#define WRITE_BUFFER                0x38
#define READ_BUFFER                 0x3C
#define READ_LONG                   0x3E
#define WRITE_LONG                  0x3F
#define MODE_SELECT                 0x55
#define MODE_SENSE                  0x5A
#define READ_12                     0xA8
#define WRITE_12                    0xAA
#define MAX_ATAPI_BYTE_COUNT        (0xfffe)

//
// Sense Key
//
#define REQUEST_SENSE_ERROR (0x70)
#define SK_NO_SENSE         (0x0)
#define SK_RECOVERY_ERROR   (0x1)
#define SK_NOT_READY        (0x2)
#define SK_MEDIUM_ERROR     (0x3)
#define SK_HARDWARE_ERROR   (0x4)
#define SK_ILLEGAL_REQUEST  (0x5)
#define SK_UNIT_ATTENTION   (0x6)
#define SK_DATA_PROTECT     (0x7)
#define SK_BLANK_CHECK      (0x8)
#define SK_VENDOR_SPECIFIC  (0x9)
#define SK_RESERVED_A       (0xA)
#define SK_ABORT            (0xB)
#define SK_RESERVED_C       (0xC)
#define SK_OVERFLOW         (0xD)
#define SK_MISCOMPARE       (0xE)
#define SK_RESERVED_F       (0xF)

//
// Additional Sense Codes
//
#define ASC_NOT_READY                   (0x04)
#define ASC_MEDIA_ERR1                  (0x10)
#define ASC_MEDIA_ERR2                  (0x11)
#define ASC_MEDIA_ERR3                  (0x14)
#define ASC_MEDIA_ERR4                  (0x30)
#define ASC_MEDIA_UPSIDE_DOWN           (0x06)
#define ASC_INVALID_CMD                 (0x20)
#define ASC_LBA_OUT_OF_RANGE            (0x21)
#define ASC_INVALID_FIELD               (0x24)
#define ASC_WRITE_PROTECTED             (0x27)
#define ASC_MEDIA_CHANGE                (0x28)
#define ASC_RESET                       (0x29)  /* Power On Reset or Bus Reset occurred */
#define ASC_ILLEGAL_FIELD               (0x26)
#define ASC_NO_MEDIA                    (0x3A)
#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)

//
// Additional Sense Code Qualifier
//
#define ASCQ_IN_PROGRESS  (0x01)

#define SETFEATURE        TRUE
#define CLEARFEATURE      FALSE

//
//  ATAPI Data structure
//
#pragma pack(1)

typedef struct {
  UINT8 peripheral_type;
  UINT8 RMB;
  UINT8 version;
  UINT8 response_data_format;
  UINT8 addnl_length;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 reserved_7;
  UINT8 vendor_info[8];
  UINT8 product_id[12];
  UINT8 eeprom_product_code[4];
  UINT8 firmware_rev_level[4];
  UINT8 firmware_sub_rev_level[1];
  UINT8 reserved_37;
  UINT8 reserved_38;
  UINT8 reserved_39;
  UINT8 max_capacity_hi;
  UINT8 max_capacity_mid;
  UINT8 max_capacity_lo;
  UINT8 reserved_43_95[95 - 43 + 1];
} INQUIRY_DATA;

typedef struct {
  UINT8 peripheral_type;
  UINT8 RMB;
  UINT8 version;
  UINT8 response_data_format;
  UINT8 addnl_length;
  UINT8 reserved_5;
  UINT8 reserved_6;
  UINT8 reserved_7;
  UINT8 vendor_info[8];
  UINT8 product_id[16];
  UINT8 product_revision_level[4];
  UINT8 vendor_specific[20];
  UINT8 reserved_56_95[40];
} CDROM_INQUIRY_DATA;

typedef struct {
  UINT8 error_code : 7;
  UINT8 valid : 1;
  UINT8 reserved_1;
  UINT8 sense_key : 4;
  UINT8 reserved_21 : 1;
  UINT8 ILI : 1;
  UINT8 reserved_22 : 2;
  UINT8 vendor_specific_3;
  UINT8 vendor_specific_4;
  UINT8 vendor_specific_5;
  UINT8 vendor_specific_6;
  UINT8 addnl_sense_length;           // n - 7
  UINT8 vendor_specific_8;
  UINT8 vendor_specific_9;
  UINT8 vendor_specific_10;
  UINT8 vendor_specific_11;
  UINT8 addnl_sense_code;             // mandatory
  UINT8 addnl_sense_code_qualifier;   // mandatory
  UINT8 field_replaceable_unit_code;  // optional
  UINT8 reserved_15;
  UINT8 reserved_16;
  UINT8 reserved_17;
  //
  // Followed by additional sense bytes     : FIXME
  //
} REQUEST_SENSE_DATA;

typedef struct {
  UINT8 LastLba3;
  UINT8 LastLba2;
  UINT8 LastLba1;
  UINT8 LastLba0;
  UINT8 BlockSize3;
  UINT8 BlockSize2;
  UINT8 BlockSize1;
  UINT8 BlockSize0;
} READ_CAPACITY_DATA;

typedef struct {
  UINT8 reserved_0;
  UINT8 reserved_1;
  UINT8 reserved_2;
  UINT8 Capacity_Length;
  UINT8 LastLba3;
  UINT8 LastLba2;
  UINT8 LastLba1;
  UINT8 LastLba0;
  UINT8 DesCode : 2;
  UINT8 reserved_9 : 6;
  UINT8 BlockSize2;
  UINT8 BlockSize1;
  UINT8 BlockSize0;
} READ_FORMAT_CAPACITY_DATA;

#pragma pack()

//
// PIO mode definition
//
typedef enum {
  ATA_PIO_MODE_BELOW_2,
  ATA_PIO_MODE_2,
  ATA_PIO_MODE_3,
  ATA_PIO_MODE_4
} ATA_PIO_MODE;

//
// Multi word DMA definition
//
typedef enum {
  ATA_MDMA_MODE_0,
  ATA_MDMA_MODE_1,
  ATA_MDMA_MODE_2
} ATA_MDMA_MODE;

//
// UDMA mode definition
//
typedef enum {
  ATA_UDMA_MODE_0,
  ATA_UDMA_MODE_1,
  ATA_UDMA_MODE_2,
  ATA_UDMA_MODE_3,
  ATA_UDMA_MODE_4,
  ATA_UDMA_MODE_5
} ATA_UDMA_MODE;

#define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
#define ATA_MODE_CATEGORY_FLOW_PIO    0x01
#define ATA_MODE_CATEGORY_MDMA        0x04
#define ATA_MODE_CATEGORY_UDMA        0x08

#pragma pack(1)

typedef struct {
  UINT8 ModeNumber : 3;
  UINT8 ModeCategory : 5;
} ATA_TRANSFER_MODE;

typedef struct {
  UINT8 Sector;
  UINT8 Heads;
  UINT8 MultipleSector;
} ATA_DRIVE_PARMS;

#pragma pack()
//
// IORDY Sample Point field value
//
#define ISP_5_CLK 0
#define ISP_4_CLK 1
#define ISP_3_CLK 2
#define ISP_2_CLK 3

//
// Recovery Time field value
//
#define RECVY_4_CLK 0
#define RECVY_3_CLK 1
#define RECVY_2_CLK 2
#define RECVY_1_CLK 3

//
// Slave IDE Timing Register Enable
//
#define SITRE bit14

//
// DMA Timing Enable Only Select 1
//
#define DTE1  bit7

//
// Pre-fetch and Posting Enable Select 1
//
#define PPE1  bit6

//
// IORDY Sample Point Enable Select 1
//
#define IE1 bit5

//
// Fast Timing Bank Drive Select 1
//
#define TIME1 bit4

//
// DMA Timing Enable Only Select 0
//
#define DTE0  bit3

//
// Pre-fetch and Posting Enable Select 0
//
#define PPE0  bit2

//
// IOREY Sample Point Enable Select 0
//
#define IE0 bit1

//
// Fast Timing Bank Drive Select 0
//
#define TIME0 bit0

#endif