uhci.h
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2,654 行
/*++
Copyright (c) 2004 - 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Uhci.h
Abstract:
Revision History
--*/
#ifndef _UHCI_H
#define _UHCI_H
/*
* Universal Host Controller Interface data structures and defines
*/
#include "Tiano.h"
#include "EfiDriverLib.h"
#include "pci22.h"
//
// Driver Consumed Protocol Prototypes
//
#include EFI_PROTOCOL_DEFINITION (DriverBinding)
#include EFI_PROTOCOL_DEFINITION (PciIo)
//
// Driver Produced Protocol Prototypes
//
#include EFI_PROTOCOL_DEFINITION (UsbHostController)
#include EFI_PROTOCOL_DEFINITION (ComponentName)
#define EFI_D_UHCI EFI_D_INFO
//
// stall time
//
#define STALL_1_MILLI_SECOND 1000
#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
#define FORCE_GLOBAL_RESUME_TIME 20 * STALL_1_MILLI_SECOND
#define ROOT_PORT_REST_TIME 50 * STALL_1_MILLI_SECOND
#define PORT_RESET_RECOVERY_TIME 10 * STALL_1_MILLI_SECOND
//
// 50 ms
//
#define INTERRUPT_POLLING_TIME 50 * 1000 * 10
//
// UHCI IO Space Address Register Register locates at
// offset 20 ~ 23h of PCI Configuration Space (UHCI spec, Revision 1.1),
// so, its BAR Index is 4.
//
#define USB_BAR_INDEX 4
//
// One memory block uses 1 page (common buffer for QH,TD use.)
//
#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
#define bit(a) (1 << (a))
//
// ////////////////////////////////////////////////////////////////////////
//
// Universal Host Controller Registers Definitions
//
//////////////////////////////////////////////////////////////////////////
extern UINT16 USBBaseAddr;
/* Command register */
#define USBCMD 0 /* Command Register Offset 00-01h */
#define USBCMD_RS bit (0) /* Run/Stop */
#define USBCMD_HCRESET bit (1) /* Host reset */
#define USBCMD_GRESET bit (2) /* Global reset */
#define USBCMD_EGSM bit (3) /* Global Suspend Mode */
#define USBCMD_FGR bit (4) /* Force Global Resume */
#define USBCMD_SWDBG bit (5) /* SW Debug mode */
#define USBCMD_CF bit (6) /* Config Flag (sw only) */
#define USBCMD_MAXP bit (7) /* Max Packet (0 = 32, 1 = 64) */
/* Status register */
#define USBSTS 2 /* Status Register Offset 02-03h */
#define USBSTS_USBINT bit (0) /* Interrupt due to IOC */
#define USBSTS_ERROR bit (1) /* Interrupt due to error */
#define USBSTS_RD bit (2) /* Resume Detect */
#define USBSTS_HSE bit (3) /* Host System Error*/
#define USBSTS_HCPE bit (4) /* Host Controller Process Error*/
#define USBSTS_HCH bit (5) /* HC Halted */
/* Interrupt enable register */
#define USBINTR 4 /* Interrupt Enable Register 04-05h */
#define USBINTR_TIMEOUT bit (0) /* Timeout/CRC error enable */
#define USBINTR_RESUME bit (1) /* Resume interrupt enable */
#define USBINTR_IOC bit (2) /* Interrupt On Complete enable */
#define USBINTR_SP bit (3) /* Short packet interrupt enable */
/* Frame Number Register Offset 06-08h */
#define USBFRNUM 6
/* Frame List Base Address Register Offset 08-0Bh */
#define USBFLBASEADD 8
/* Start of Frame Modify Register Offset 0Ch */
#define USBSOF 0x0c
/* USB port status and control registers */
#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
#define USBPORTSC_CCS bit (0) /* Current Connect Status*/
#define USBPORTSC_CSC bit (1) /* Connect Status Change */
#define USBPORTSC_PED bit (2) /* Port Enable / Disable */
#define USBPORTSC_PEDC bit (3) /* Port Enable / Disable Change */
#define USBPORTSC_LSL bit (4) /* Line Status Low bit*/
#define USBPORTSC_LSH bit (5) /* Line Status High bit*/
#define USBPORTSC_RD bit (6) /* Resume Detect */
#define USBPORTSC_LSDA bit (8) /* Low Speed Device Attached */
#define USBPORTSC_PR bit (9) /* Port Reset */
#define USBPORTSC_SUSP bit (12) /* Suspend */
/* PCI Configuration Registers for USB */
//
// Class Code Register offset
//
#define CLASSC 0x09
//
// USB IO Space Base Address Register offset
//
#define USBBASE 0x20
//
// USB legacy Support
//
#define USB_EMULATION 0xc0
//
// USB Base Class Code,Sub-Class Code and Programming Interface.
//
#define PCI_CLASSC_PI_UHCI 0x00
#define SETUP_PACKET_ID 0x2D
#define INPUT_PACKET_ID 0x69
#define OUTPUT_PACKET_ID 0xE1
#define ERROR_PACKET_ID 0x55
//
// ////////////////////////////////////////////////////////////////////////
//
// USB Transfer Mechanism Data Structures
//
//////////////////////////////////////////////////////////////////////////
#pragma pack(1)
//
// USB Class Code structure
//
typedef struct {
UINT8 PI;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
UINT32 QHHorizontalTerminate : 1;
UINT32 QHHorizontalQSelect : 1;
UINT32 QHHorizontalRsvd : 2;
UINT32 QHHorizontalPtr : 28;
UINT32 QHVerticalTerminate : 1;
UINT32 QHVerticalQSelect : 1;
UINT32 QHVerticalRsvd : 2;
UINT32 QHVerticalPtr : 28;
} QUEUE_HEAD;
typedef struct {
UINT32 TDLinkPtrTerminate : 1;
UINT32 TDLinkPtrQSelect : 1;
UINT32 TDLinkPtrDepthSelect : 1;
UINT32 TDLinkPtrRsvd : 1;
UINT32 TDLinkPtr : 28;
UINT32 TDStatusActualLength : 11;
UINT32 TDStatusRsvd : 5;
UINT32 TDStatus : 8;
UINT32 TDStatusIOC : 1;
UINT32 TDStatusIOS : 1;
UINT32 TDStatusLS : 1;
UINT32 TDStatusErr : 2;
UINT32 TDStatusSPD : 1;
UINT32 TDStatusRsvd2 : 2;
UINT32 TDTokenPID : 8;
UINT32 TDTokenDevAddr : 7;
UINT32 TDTokenEndPt : 4;
UINT32 TDTokenDataToggle : 1;
UINT32 TDTokenRsvd : 1;
UINT32 TDTokenMaxLen : 11;
UINT32 TDBufferPtr;
} TD;
#pragma pack()
typedef struct {
QUEUE_HEAD QH;
VOID *ptrNext;
VOID *ptrDown;
VOID *ptrNextIntQH; // for interrupt transfer's special use
VOID *LoopPtr;
} QH_STRUCT;
typedef struct {
TD TDData;
UINT8 *pTDBuffer;
VOID *ptrNextTD;
VOID *ptrNextQH;
UINT16 TDBufferLength;
UINT16 reserved;
} TD_STRUCT;
//
// ////////////////////////////////////////////////////////////////////////
//
// Universal Host Controller Device Data Structure
//
//////////////////////////////////////////////////////////////////////////
#define USB_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)
#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
#define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
#define INTERRUPT_LIST_SIGNATURE EFI_SIGNATURE_32 ('i', 'n', 't', 's')
typedef struct {
UINTN Signature;
EFI_LIST_ENTRY Link;
UINT8 DevAddr;
UINT8 EndPoint;
UINT8 DataToggle;
UINT8 Reserved[5];
TD_STRUCT *PtrFirstTD;
QH_STRUCT *PtrQH;
UINTN DataLen;
UINTN PollInterval;
VOID *Mapping;
UINT8 *DataBuffer; // allocated host memory, not mapped memory
EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack;
VOID *InterruptContext;
} INTERRUPT_LIST;
#define INTERRUPT_LIST_FROM_LINK(a) CR (a, INTERRUPT_LIST, Link, INTERRUPT_LIST_SIGNATURE)
typedef struct {
UINT32 FrameListPtrTerminate : 1;
UINT32 FrameListPtrQSelect : 1;
UINT32 FrameListRsvd : 2;
UINT32 FrameListPtr : 28;
} FRAMELIST_ENTRY;
typedef struct _MEMORY_MANAGE_HEADER {
UINT8 *BitArrayPtr;
UINTN BitArraySizeInBytes;
UINT8 *MemoryBlockPtr;
UINTN MemoryBlockSizeInBytes;
VOID *Mapping;
struct _MEMORY_MANAGE_HEADER *Next;
} MEMORY_MANAGE_HEADER;
typedef struct {
UINTN Signature;
EFI_USB_HC_PROTOCOL UsbHc;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_PCI_IO_PROTOCOL *PciIo;
//
// local data
//
EFI_LIST_ENTRY InterruptListHead;
FRAMELIST_ENTRY *FrameListEntry;
VOID *FrameListMapping;
MEMORY_MANAGE_HEADER *MemoryHeader;
EFI_EVENT InterruptTransTimer;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
} USB_HC_DEV;
extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;
EFI_STATUS
WriteUHCCommandReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 CmdAddrOffset,
IN UINT16 UsbCmd
)
/*++
Routine Description:
Write UHCI Command Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
CmdAddrOffset - Command address offset
UsbCmd - Data to write
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
ReadUHCCommandReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 CmdAddrOffset,
IN OUT UINT16 *Data
)
/*++
Routine Description:
Read UHCI Command Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
CmdAddrOffset - Command address offset
Data - Data to return
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
WriteUHCStatusReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusAddrOffset,
IN UINT16 UsbSts
)
/*++
Routine Description:
Write UHCI Staus Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusAddrOffset - Status address offset
UsbSts - Data to write
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
ReadUHCStatusReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusAddrOffset,
IN OUT UINT16 *Data
)
/*++
Routine Description:
Read UHCI Staus Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusAddrOffset - Status address offset
UsbSts - Data to return
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
ClearStatusReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusAddrOffset
)
/*++
Routine Description:
Clear the content of UHC's Status Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusAddrOffset - Status address offset
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
ReadUHCFrameNumberReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 FrameNumAddrOffset,
IN OUT UINT16 *Data
)
/*++
Routine Description:
Read from UHC's Frame Number Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
FrameNumAddrOffset - Frame number register offset
Data - Data to return
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
WriteUHCFrameListBaseReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 FlBaseAddrOffset,
IN UINT32 UsbFrameListBaseAddr
)
/*++
Routine Description:
Write to UHC's Frame List Base Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
FlBaseAddrOffset - Frame Base address register
UsbFrameListBaseAddr - Address to write
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
ReadRootPortReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 PortAddrOffset,
IN OUT UINT16 *Data
)
/*++
Routine Description:
Read from UHC's Root Port Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
PortAddrOffset - Port Addrress Offset,
Data - Data to return
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
WriteRootPortReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 PortAddrOffset,
IN UINT16 ControlBits
)
/*++
Routine Description:
Write to UHC's Root Port Register
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
PortAddrOffset - Port Addrress Offset,
ControlBits - Data to write
Returns:
EFI_SUCCESS
--*/
;
EFI_STATUS
WaitForUHCHalt (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusRegAddr,
IN UINTN Timeout
)
/*++
Routine Description:
Wait until UHCI halt or timeout
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusRegAddr - Status Register Address
Timeout - Time out value in us
Returns:
EFI_DEVICE_ERROR - Unable to read the status register
EFI_TIMEOUT - Time out
EFI_SUCCESS - Success
--*/
;
BOOLEAN
IsStatusOK (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusRegAddr
)
/*++
Routine Description:
Judge whether the host controller operates well
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusRegAddr - Status register address
Returns:
TRUE - Status is good
FALSE - Status is bad
--*/
;
BOOLEAN
IsHostSysOrProcessErr (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 StatusRegAddr
)
/*++
Routine Description:
Judge the status is HostSys,ProcessErr error or good
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
StatusRegAddr - Status register address
Returns:
TRUE - Status is good
FALSE - Status is bad
--*/
;
UINT16
GetCurrentFrameNumber (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 FrameNumAddrOffset
)
/*++
Routine Description:
Get Current Frame Number
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
FrameNumAddrOffset - FrameNum register AddrOffset
Returns:
Frame number
--*/
;
EFI_STATUS
SetFrameListBaseAddress (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 FLBASEADDRReg,
IN UINT32 Addr
)
/*++
Routine Description:
Set FrameListBase Address
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
FlBaseAddrReg - FrameListBase register
Addr - Address to set
Returns:
EFI_SUCCESS
--*/
;
UINT32
GetFrameListBaseAddress (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 FLBAddr
)
/*++
Routine Description:
Get Current Frame Number
Arguments:
PciIo - EFI_PCI_IO_PROTOCOL
FrameNumAddrOffset - FrameNum register AddrOffset
Returns:
Frame number
--*/
;
EFI_STATUS
CreateFrameList (
IN USB_HC_DEV *HcDev,
IN UINT32 FLBASEADDRReg
)
/*++
Routine Description:
CreateFrameList
Arguments:
HcDev - USB_HC_DEV
FlBaseAddrReg - Frame List register
Returns:
EFI_OUT_OF_RESOURCES - Can't allocate memory resources
EFI_UNSUPPORTED - Map memory fail
EFI_SUCCESS - Success
--*/
;
EFI_STATUS
FreeFrameListEntry (
IN USB_HC_DEV *UhcDev
)
/*++
Routine Description:
Free FrameList buffer
Arguments:
HcDev - USB_HC_DEV
Returns:
EFI_SUCCESS - success
--*/
;
VOID
InitFrameList (
IN USB_HC_DEV *HcDev
)
/*++
Routine Description:
Initialize FrameList
Arguments:
HcDev - USB_HC_DEV
Returns:
VOID
--*/
;
EFI_STATUS
CreateQH (
IN USB_HC_DEV *HcDev,
OUT QH_STRUCT **pptrQH
)
/*++
Routine Description:
CreateQH
Arguments:
HcDev - USB_HC_DEV
pptrQH - QH_STRUCT content to return
Returns:
EFI_SUCCESS - Success
EFI_OUT_OF_RESOURCES - Can't allocate memory
--*/
;
VOID
SetQHHorizontalLinkPtr (
IN QH_STRUCT *ptrQH,
IN VOID *ptrNext
)
/*++
Routine Description:
Set QH Horizontal Link Pointer
Arguments:
PtrQH - QH_STRUCT
ptrNext - Data to write
Returns:
VOID
--*/
;
VOID *
GetQHHorizontalLinkPtr (
IN QH_STRUCT *ptrQH
)
/*++
Routine Description:
Get QH Horizontal Link Pointer
Arguments:
PtrQH - QH_STRUCT
Returns:
Data to return
--*/
;
VOID
SetQHHorizontalQHorTDSelect (
IN QH_STRUCT *ptrQH,
IN BOOLEAN bQH
)
/*++
Routine Description:
Set QH Horizontal QH or TD
Arguments:
PtrQH - QH_STRUCT
bQH - TRUE is QH FALSE is TD
Returns:
VOID
--*/
;
VOID
SetQHHorizontalValidorInvalid (
IN QH_STRUCT *ptrQH,
IN BOOLEAN bValid
)
/*++
Routine Description:
Set QH Horizontal Valid or Invalid
Arguments:
PtrQH - QH_STRUCT
bValid - TRUE is Valid FALSE is Invalid
Returns:
VOID
--*/
;
VOID
SetQHVerticalLinkPtr (
IN QH_STRUCT *ptrQH,
IN VOID *ptrNext
)
/*++
Routine Description:
Set QH Vertical Link Pointer
Arguments:
PtrQH - QH_STRUCT
ptrNext - Data to write
Returns:
VOID
--*/
;
VOID *
GetQHVerticalLinkPtr (
IN QH_STRUCT *ptrQH
)
/*++
Routine Description:
Get QH Vertical Link Pointer
Arguments:
PtrQH - QH_STRUCT
Returns:
Data to return
--*/
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