pci22.h
来自「EFI BIOS是Intel提出的下一代的BIOS标准。这里上传的Edk源代码是」· C头文件 代码 · 共 557 行 · 第 1/2 页
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#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
#define HEADER_TYPE_DEVICE 0x00
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
#define HEADER_TYPE_MULTI_FUNCTION 0x80
#define HEADER_LAYOUT_CODE 0x7f
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
#define PCI_DEVICE_ROMBAR 0x30
#define PCI_BRIDGE_ROMBAR 0x38
#define PCI_MAX_BAR 0x0006
#define PCI_MAX_CONFIG_OFFSET 0x0100
#define PCI_VENDOR_ID_OFFSET 0x00
#define PCI_DEVICE_ID_OFFSET 0x02
#define PCI_COMMAND_OFFSET 0x04
#define PCI_PRIMARY_STATUS_OFFSET 0x06
#define PCI_REVISION_ID_OFFSET 0x08
#define PCI_CLASSCODE_OFFSET 0x09
#define PCI_CACHELINE_SIZE_OFFSET 0x0C
#define PCI_LATENCY_TIMER_OFFSET 0x0D
#define PCI_HEADER_TYPE_OFFSET 0x0E
#define PCI_BIST_OFFSET 0x0F
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
#define PCI_CARDBUS_CIS_OFFSET 0x28
#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
#define PCI_SID_OFFSET 0x2E // SubSystem ID
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
#define PCI_EXPANSION_ROM_BASE 0x30
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
//
// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
//
#define PCI_INT_LINE_UNKNOWN 0xFF
typedef struct {
UINT32 Reg : 8;
UINT32 Func : 3;
UINT32 Dev : 5;
UINT32 Bus : 8;
UINT32 Reserved : 7;
UINT32 Enable : 1;
} PCI_CONFIG_ACCESS_CF8;
#pragma pack()
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
#define PCI_CODE_TYPE_EFI_IMAGE 0x03
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
#define EFI_PCI_COMMAND_IO_SPACE 0x0001
#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
#define EFI_PCI_COMMAND_SERR 0x0100
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
//
// Following are the PCI-CARDBUS bridge control bit
//
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
//
// Following are the PCI status control bit
//
#define EFI_PCI_STATUS_CAPABILITY 0x0010
#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
#define EFI_PCI_CAPABILITY_PTR 0x34
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
#pragma pack(1)
typedef struct {
UINT16 Signature; // 0xaa55
UINT8 Reserved[0x16];
UINT16 PcirOffset;
} PCI_EXPANSION_ROM_HEADER;
typedef struct {
UINT16 Signature; // 0xaa55
UINT8 Size512;
UINT8 InitEntryPoint[3];
UINT8 Reserved[0x12];
UINT16 PcirOffset;
} EFI_LEGACY_EXPANSION_ROM_HEADER;
typedef struct {
UINT32 Signature; // "PCIR"
UINT16 VendorId;
UINT16 DeviceId;
UINT16 Reserved0;
UINT16 Length;
UINT8 Revision;
UINT8 ClassCode[3];
UINT16 ImageLength;
UINT16 CodeRevision;
UINT8 CodeType;
UINT8 Indicator;
UINT16 Reserved1;
} PCI_DATA_STRUCTURE;
//
// PCI Capability List IDs and records
//
#define EFI_PCI_CAPABILITY_ID_PMI 0x01
#define EFI_PCI_CAPABILITY_ID_AGP 0x02
#define EFI_PCI_CAPABILITY_ID_VPD 0x03
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
typedef struct {
UINT8 CapabilityID;
UINT8 NextItemPtr;
} EFI_PCI_CAPABILITY_HDR;
//
// Capability EFI_PCI_CAPABILITY_ID_PMI
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 PMC;
UINT16 PMCSR;
UINT8 BridgeExtention;
UINT8 Data;
} EFI_PCI_CAPABILITY_PMI;
//
// Capability EFI_PCI_CAPABILITY_ID_AGP
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT8 Rev;
UINT8 Reserved;
UINT32 Status;
UINT32 Command;
} EFI_PCI_CAPABILITY_AGP;
//
// Capability EFI_PCI_CAPABILITY_ID_VPD
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 AddrReg;
UINT32 DataReg;
} EFI_PCI_CAPABILITY_VPD;
//
// Capability EFI_PCI_CAPABILITY_ID_SLOTID
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT8 ExpnsSlotReg;
UINT8 ChassisNo;
} EFI_PCI_CAPABILITY_SLOTID;
//
// Capability EFI_PCI_CAPABILITY_ID_MSI
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 MsgCtrlReg;
UINT32 MsgAddrReg;
UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI32;
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 MsgCtrlReg;
UINT32 MsgAddrRegLsdw;
UINT32 MsgAddrRegMsdw;
UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI64;
//
// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
//
// not finished - fields need to go here
//
} EFI_PCI_CAPABILITY_HOTPLUG;
//
// Capability EFI_PCI_CAPABILITY_ID_PCIX
//
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 CommandReg;
UINT32 StatusReg;
} EFI_PCI_CAPABILITY_PCIX;
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 SecStatusReg;
UINT32 StatusReg;
UINT32 SplitTransCtrlRegUp;
UINT32 SplitTransCtrlRegDn;
} EFI_PCI_CAPABILITY_PCIX_BRDG;
#define DEVICE_ID_NOCARE 0xFFFF
#define PCI_ACPI_UNUSED 0
#define PCI_BAR_NOCHANGE 0
#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFF
#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFE
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC
#define PCI_BAR_IDX0 0x00
#define PCI_BAR_IDX1 0x01
#define PCI_BAR_IDX2 0x02
#define PCI_BAR_IDX3 0x03
#define PCI_BAR_IDX4 0x04
#define PCI_BAR_IDX5 0x05
#define PCI_BAR_ALL 0xFF
#pragma pack(pop)
//
// NOTE: The following header files are included here for
// compatibility consideration.
//
#include "pci23.h"
#include "pci30.h"
#include "EfiPci.h"
#endif
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