pci22.h
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/*++
Copyright (c) 2004 - 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
pci22.h
Abstract:
Support for PCI 2.2 standard.
Revision History
--*/
#ifndef _PCI22_H
#define _PCI22_H
#define PCI_MAX_SEGMENT 0
#define PCI_MAX_BUS 255
#define PCI_MAX_DEVICE 31
#define PCI_MAX_FUNC 7
//
// Command
//
#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
#pragma pack(push, 1)
typedef struct {
UINT16 VendorId;
UINT16 DeviceId;
UINT16 Command;
UINT16 Status;
UINT8 RevisionID;
UINT8 ClassCode[3];
UINT8 CacheLineSize;
UINT8 LatencyTimer;
UINT8 HeaderType;
UINT8 BIST;
} PCI_DEVICE_INDEPENDENT_REGION;
typedef struct {
UINT32 Bar[6];
UINT32 CISPtr;
UINT16 SubsystemVendorID;
UINT16 SubsystemID;
UINT32 ExpansionRomBar;
UINT8 CapabilityPtr;
UINT8 Reserved1[3];
UINT32 Reserved2;
UINT8 InterruptLine;
UINT8 InterruptPin;
UINT8 MinGnt;
UINT8 MaxLat;
} PCI_DEVICE_HEADER_TYPE_REGION;
typedef struct {
PCI_DEVICE_INDEPENDENT_REGION Hdr;
PCI_DEVICE_HEADER_TYPE_REGION Device;
} PCI_TYPE00;
typedef struct {
UINT32 Bar[2];
UINT8 PrimaryBus;
UINT8 SecondaryBus;
UINT8 SubordinateBus;
UINT8 SecondaryLatencyTimer;
UINT8 IoBase;
UINT8 IoLimit;
UINT16 SecondaryStatus;
UINT16 MemoryBase;
UINT16 MemoryLimit;
UINT16 PrefetchableMemoryBase;
UINT16 PrefetchableMemoryLimit;
UINT32 PrefetchableBaseUpper32;
UINT32 PrefetchableLimitUpper32;
UINT16 IoBaseUpper16;
UINT16 IoLimitUpper16;
UINT8 CapabilityPtr;
UINT8 Reserved[3];
UINT32 ExpansionRomBAR;
UINT8 InterruptLine;
UINT8 InterruptPin;
UINT16 BridgeControl;
} PCI_BRIDGE_CONTROL_REGISTER;
typedef struct {
PCI_DEVICE_INDEPENDENT_REGION Hdr;
PCI_BRIDGE_CONTROL_REGISTER Bridge;
} PCI_TYPE01;
typedef union {
PCI_TYPE00 Device;
PCI_TYPE01 Bridge;
} PCI_TYPE_GENERIC;
typedef struct {
UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
// Address Register
//
UINT16 Reserved;
UINT16 SecondaryStatus; // Secondary Status
UINT8 PciBusNumber; // PCI Bus Number
UINT8 CardBusBusNumber; // CardBus Bus Number
UINT8 SubordinateBusNumber; // Subordinate Bus Number
UINT8 CardBusLatencyTimer; // CardBus Latency Timer
UINT32 MemoryBase0; // Memory Base Register 0
UINT32 MemoryLimit0; // Memory Limit Register 0
UINT32 MemoryBase1;
UINT32 MemoryLimit1;
UINT32 IoBase0;
UINT32 IoLimit0; // I/O Base Register 0
UINT32 IoBase1; // I/O Limit Register 0
UINT32 IoLimit1;
UINT8 InterruptLine; // Interrupt Line
UINT8 InterruptPin; // Interrupt Pin
UINT16 BridgeControl; // Bridge Control
} PCI_CARDBUS_CONTROL_REGISTER;
//
// Definitions of PCI class bytes and manipulation macros.
//
#define PCI_CLASS_OLD 0x00
#define PCI_CLASS_OLD_OTHER 0x00
#define PCI_CLASS_OLD_VGA 0x01
#define PCI_CLASS_MASS_STORAGE 0x01
#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
#define PCI_CLASS_IDE 0x01
#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
#define PCI_CLASS_MASS_STORAGE_IPI 0x03
#define PCI_CLASS_MASS_STORAGE_RAID 0x04
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x00
#define PCI_CLASS_ETHERNET 0x00 // obsolete
#define PCI_CLASS_NETWORK_TOKENRING 0x01
#define PCI_CLASS_NETWORK_FDDI 0x02
#define PCI_CLASS_NETWORK_ATM 0x03
#define PCI_CLASS_NETWORK_ISDN 0x04
#define PCI_CLASS_NETWORK_OTHER 0x80
#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
#define PCI_CLASS_DISPLAY_VGA 0x00
#define PCI_CLASS_VGA 0x00 // obsolete
#define PCI_CLASS_DISPLAY_XGA 0x01
#define PCI_CLASS_DISPLAY_3D 0x02
#define PCI_CLASS_DISPLAY_OTHER 0x80
#define PCI_CLASS_DISPLAY_GFX 0x80
#define PCI_CLASS_GFX 0x80 // obsolete
#define PCI_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x00
#define PCI_CLASS_BRIDGE_ISA 0x01
#define PCI_CLASS_ISA 0x01 // obsolete
#define PCI_CLASS_BRIDGE_EISA 0x02
#define PCI_CLASS_BRIDGE_MCA 0x03
#define PCI_CLASS_BRIDGE_P2P 0x04
#define PCI_CLASS_BRIDGE_PCMCIA 0x05
#define PCI_CLASS_BRIDGE_NUBUS 0x06
#define PCI_CLASS_BRIDGE_CARDBUS 0x07
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
#define PCI_CLASS_SCC 0x07 // Simple communications controllers
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
#define PCI_IF_16550 0x02
#define PCI_IF_16650 0x03
#define PCI_IF_16750 0x04
#define PCI_IF_16850 0x05
#define PCI_IF_16950 0x06
#define PCI_SUBCLASS_PARALLEL 0x01
#define PCI_IF_PARALLEL_PORT 0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
#define PCI_IF_ECP_PARALLEL_PORT 0x02
#define PCI_IF_1284_CONTROLLER 0x03
#define PCI_IF_1284_DEVICE 0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
#define PCI_SUBCLASS_MODEM 0x03
#define PCI_IF_GENERIC_MODEM 0x00
#define PCI_IF_16450_MODEM 0x01
#define PCI_IF_16550_MODEM 0x02
#define PCI_IF_16650_MODEM 0x03
#define PCI_IF_16750_MODEM 0x04
#define PCI_SUBCLASS_OTHER 0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
#define PCI_SUBCLASS_PIC 0x00
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_TIMER 0x02
#define PCI_IF_8254_TIMER 0x00
#define PCI_IF_ISA_TIMER 0x01
#define PCI_EISA_TIMER 0x02
#define PCI_SUBCLASS_RTC 0x03
#define PCI_IF_GENERIC_RTC 0x00
#define PCI_IF_ISA_RTC 0x00
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
#define PCI_CLASS_INPUT_DEVICE 0x09
#define PCI_SUBCLASS_KEYBOARD 0x00
#define PCI_SUBCLASS_PEN 0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
#define PCI_SUBCLASS_GAMEPORT 0x04
#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_CLASS_PROCESSOR 0x0B
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_MIPS 0x30
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
#define PCI_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
#define PCI_CLASS_SERIAL_SSA 0x02
#define PCI_CLASS_SERIAL_USB 0x03
#define PCI_IF_EHCI 0x20
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
#define PCI_CLASS_SERIAL_SMB 0x05
#define PCI_CLASS_WIRELESS 0x0D
#define PCI_SUBCLASS_IRDA 0x00
#define PCI_SUBCLASS_IR 0x01
#define PCI_SUBCLASS_RF 0x02
#define PCI_CLASS_INTELLIGENT_IO 0x0E
#define PCI_CLASS_SATELLITE 0x0F
#define PCI_SUBCLASS_TV 0x01
#define PCI_SUBCLASS_AUDIO 0x02
#define PCI_SUBCLASS_VOICE 0x03
#define PCI_SUBCLASS_DATA 0x04
#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
#define PCI_SUBCLASS_NET_COMPUT 0x00
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_CLASS_DPIO 0x11
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
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