video_test.h

ADSP 地层驱动

/////////////////////////////////////////////////////
// Video_test.h
//
//
//
/////////////////////////////////////////////////////
#ifndef _VIDEO_TEST_H_
#define _VIDEO_TEST_H_

#define TIME_OUT	0x1000000

#define PIXEL_PER_LINE 		(720)
#define LINES_PER_FRAME		(480)
#define TOTAL_SDRAM_USED	(PIXEL_PER_LINE * LINES_PER_FRAME * 2)
#define COLORBAR_START		0x0

////////////////////////////////////////////////////////
//valuable for flash configure
/////////////////////////////////////////////////////////
//all banks enabled
#define en_async_mem 0xf

//all banks are configured in: 
//4 cycles transition time; 3 cycles setup time; 2 cycles hold time; 
//11 cycles read access time; 7 cycles write access time
#define AMB0_TIMING 0x7bb07bb0
#define AMB1_TIMING 0x7bb07bb0

// addresses for Port B in Flash A
#define pFlashA_Data_Out	(volatile unsigned char *)0x20270004
#define pFlashB_Data_Out	(volatile unsigned char *)0x20270005
#define pFlashA_Data_Dir	(volatile unsigned char *)0x20270006
#define pFlashB_Data_Dir	(volatile unsigned char *)0x20270007


#define flashA_sram 0x20240000	// base addr
#define flashA_csio 0x20270000	// base addr
#define portA_data_out 0x04	    // reg offset
#define portB_data_out 0x05	    // reg offset
#define portA_data_dir 0x06	    // reg offset
#define portB_data_dir 0x07	    // reg offset

#define SCL 0x1                 // serial clock is PF0
#define SDA 0x2                 // serial data is PF1

#define RST_7171 0x4            // ecoder reset bit #2 in flashA portA
#define RST_7183 0x8            // decoder reset bit #3 in flashA portA
#define PPICLK_7183 0x10         // decoder's PPI clock sel bit #4 in flashA portA


#define MEM_SIZE			0x00800000	// 8MLWords
#define SDRAM_START_ADDR 	0x00000000


#define dma0_cfg_xfer8 0x12    // dma0 config for 2-D 8-bit xfer
#define dma0_cfg_xfer16 0x16   // dma0 config for 2-D 16-bit xfer
#define dma0_cfg_xfer32 0x1A   // dma0 config for 2-D 32-bit xfer

#define XCNT32_frame 0x01AD    // frame 429 x 32-bit (1716 bytes)
#define XCNT32_video 0x0168    // video 360 x 32-bit (1440 bytes)
#define XMOD32       0x4       // 32-bit xfer

#define XCNT16_frame 0x035A    // frame 858 x 16-bit (1716 bytes)
#define XCNT16_video 0x02d0    // video 720 x 16-bit (1440 bytes)
#define XMOD16       0x2       // 16-bit xfer

#define XCNT8_frame 0x06B4     // frame 1716 x 8-bit
#define XCNT8_video 0x05A0     // video 1440 x 8-bit (1440 bytes)
#define XMOD8   0x1            // 8-bit xfer


#define YCNT_2frame 0x0500     // 2 frames plus x 525 lines w/ blanking
#define YCNT_frame 0x020D      // 525 lines w/ blanking
#define YCNT_video 0x01e7      // 528-38-487 video activev only
#define YMOD32 0x4             // 32-bit xfer
#define YMOD16 0x2             // 16-bit xfer
#define YMOD8 0x1              // 8-bit xfer

#define YMOD8_2k_video 0x261   // 8-bit xfer, video,2k-1440+1=629
#define YMOD16_2k_video 0x262  // 16-bit xfer,frame,2k-1440+2=630
#define YMOD16_2k_frame 0x14e  // 16-bit xfer,frame,2k-1716+2=334
#define YMOD32_2k_video 0x264  // 32-bit xfer,video,2k-1440+4=632


#define PPI_CTRL_DMA16_FRAME 		0xc4   // 16-bit entire frame

/*************** SCCB Constants  ************************************/
#define pISR_SCCB_TIMER 			(unsigned char *)0xFFE0202C	//Address of the interrupt register (EVT11 in this case)
#define pSYSTEM_MMR_HIGH_ADDRESS 	(unsigned char *)0xFFC00000	//The high address word is handled like pages
#define pCORE_MMR_HIGH_ADDRESS 		(unsigned char *)0xFFE00000	//The high address word is handled like pages
#define SCL_PERIOD 					0xB0             // scl_period >= 133MHz/(2 x 0.4MHz)
#define SCL_HIGH 					SCL_PERIOD >> 1


typedef enum _SCCB_STATE{
  	SCCB_Start_Cond0,
  	SCCB_Start_Cond1,
  	SCCB_Start_Cond2,
  	SCCB_Xmt_Data,
  	SCCB_XMT_CLK,
  	SCCB_ACK_TST,
  	SCCB_ACK_MNGR,  
    SCCB_RCV_CLK,
    SCCB_Stop_Cond1,
    SCCB_Stop_Cond2,
    SCCB_NACK_TST,
    SCCB_RCV_NACK,
    SCCB_Rcv_Data,
    SCCB_End_of_Transmission
}SCCB_STATE;

#define vline_size 				858*2               // video line size in bytes
#define vline_size32 			(vline_size >> 2) 	// video line size in 32-bit words
#define vbuff_start_line 		0             		// first line of video buffer (0,1,...)
#define vbuff_size 				0x500               // size of video buffer in number of lines
#define vbuf_start_addr 		SDRAM_START_ADDR+vline_size*vbuff_start_line

#define rd_cmd 					0x1            		// sccb interface read command
#define wr_cmd 					0x2            		// sccb inteface write command

#define ADV7171_WR 				0x54       			// write address of video encoder
#define ADV7171_RD 				0x55       			// read address of video encoder
#define ADV7171_reg_cnt 		0x1a  				// encoder register count (26 registers)
#define ADV7171_MR0 			0x0       			// mode reg 0 address of the encoder
#define ADV7171_MR1 			0x1       			// mode reg 1 address of the encoder
#define ADV7171_MR3 			0x3
#define ADV7171_MR4 			0x4
#define ADV7171_ColorBar 		0x80
#define ADV7171_MR4_YUV_Mode 	0x03
#define ADV7171_MR3_YUV_Mode 	0x10
#define ADV7171_MR3_2_CVBS_Mode 0x8

#define ADV7183_WR 				0x40         		// read address of video decoder
#define ADV7183_RD 				0x41         		// write address of video decoder
#define ADV7183_In_Control 		0x0  				// Input Control Regsiter of decoder
#define ADV7183_AVIN4 			0x3
#define ADV7183_AVIN1 			0x0
#define ADV7183_YUV_Mode 		0x9
#define ADV7183_OE_bit 			2        			// ADV7183 /OE = PF2
#define ADV7183_OE 				0x4	        		// ADV7183 /OE = PF2


typedef enum _VIDEO_TEST
{
    AVIN1_DAC_D_A,
    AVIN4_DAC_B_A
}VIDEO_TEST;

#endif //_VIDEO_TEST_H_