adav801_test.c

ADSP 地层驱动

/*****************************************************************************
**																			**
**	 Name: 	ADAV801_Test.c											        **	
**																			**
******************************************************************************
*********************************************************************************

Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved. 

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.  


Description:
			This is the source code for the Blackfin EZ-Audio Power On Self Test 
			(POST).
			
*********************************************************************************/
#include <sysreg.h>
#include <ccblkfn.h>

#include "Test_EZ_Audio.h"
#include "ADAV801_Test.h"




//////////////////////////////////////////////////////////////////////////////
// 							Globals
//////////////////////////////////////////////////////////////////////////////
volatile int g_iTxBufferSPORT0[4];
volatile int g_iRxBufferSPORT0[4];




//--------------------------------------------------------------------------//
// Function:	void InitADAV801(void)										//
//																			//
// Description:  Configure the ADAV801 ADC/DAC
//
//--------------------------------------------------------------------------//
void InitADAV801(void)
{
	int j;
	
	volatile short sCodecADAV801TxRegs[] =
	{									
		(0x0000<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0300<<1)																| b0_0,
		(0x0400<<1)								| b4_0	| b3_1	| b2_0	| b1_0	| b0_1,
		//(0x0500<<1)								| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0500<<1)								| b4_0	| b3_1	| b2_0	| b1_0	| b0_1,
		(0x0600<<1)						| b5_0	| b4_1	| b3_0	| b2_0	| b1_0	| b0_1,
		//(0x0700<<1)						| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0700<<1)						| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_1,
		(0x0900<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0A00<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0B00<<1)						| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x0C00<<1)				| b6_0	| b5_0	| b4_0	| b3_0	| b2_1	| b1_0	| b0_1,
		(0x1E00<<1)						| b5_0			| b3_0	| b2_0	| b1_0	| b0_0,
		(0x6200<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_1	| b2_0	| b1_0	| b0_1,
		(0x6300<<1)						| b5_0	| b4_0	| b3_0	| b2_0	| b1_1	| b0_0,
		(0x6400<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x6500<<1)						| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x6E00<<1)		| b7_0	| b6_0	| b5_1	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x6F00<<1)								| b4_1					| b1_0	| b0_0,
		//(0x7400<<1)		| b7_1	| b6_1	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x7400<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		//(0x7500<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x7500<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_1,
		//(0x7600<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x7600<<1)		| b7_0	| b6_0	| b5_0	| b4_0	| b3_0	| b2_0	| b1_0	| b0_1,
		//(0x7700<<1)								| b4_1	| b3_0	| b2_0	| b1_0	| b0_0,
		(0x7700<<1)								| b4_1	| b3_1	| b2_0	| b1_0	| b0_0,
		(0x7800<<1)		| b7_0	| b6_0,
		(0x7A00<<1)						| b5_0	| b4_0			| b2_0	| b1_0	| b0_0
	
						
	};

	

	*pSPI_FLG |= FLS3;
	*pSPI_BAUD = 16;
	*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;
	*pDMA5_PERIPHERAL_MAP	= 0x5000;
	*pDMA5_CONFIG = WDSIZE_16;
	*pDMA5_START_ADDR = (void*)sCodecADAV801TxRegs;
	*pDMA5_X_COUNT = sizeof(sCodecADAV801TxRegs)/sizeof(short);
	*pDMA5_X_MODIFY = 2;
	*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
	*pSPI_CTL = (*pSPI_CTL | SPE);
	for (j=0; j<0xaff0; j++) asm("nop;");
	*pSPI_CTL = 0x0000;
	*pSPI_FLG = 0xFF00;	
	
	// unconfigur DMA5
	*pDMA5_CONFIG = 0;
	*pDMA5_START_ADDR = 0;
	*pDMA5_X_COUNT = 0;
	*pDMA5_X_MODIFY = 0; 
}


//--------------------------------------------------------------------------//
// Function:	void InitADAV801(void)										//
//																			//
// Description:  Setup sport0 for ADAV801
//
//--------------------------------------------------------------------------//
void Init_Sport0(void)
{
	// Sport0 receive configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Stereo frame sync enable
	*pSPORT0_RCR1 = RFSR | LRFS | RCKFE;
	*pSPORT0_RCR2 = SLEN_24 | RXSE | RSFSE;
	
	// Sport0 transmit configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Secondary side enable, Stereo frame sync enable
	*pSPORT0_TCR1 = TFSR | LTFS | TCKFE;
	*pSPORT0_TCR2 = SLEN_24 | TXSE | TSFSE;
}

//--------------------------------------------------------------------------//
// Function:	Init_DMA													//
//																			//
// Description:	Initialize DMA1 in autobuffer mode to receive and DMA2 in	//
//				autobuffer mode to transmit									//
//--------------------------------------------------------------------------//
void Init_Sport0_DMA(void)
{
	// Set up DMA1 to receive
	// Map DMA1 to Sport0 RX
	*pDMA1_PERIPHERAL_MAP = 0x1000;
	
	// Configure DMA1
	// 32-bit transfers, Interrupt on completion, Autobuffer mode
	*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
	// Start address of data buffer
	*pDMA1_START_ADDR = (void*)g_iRxBufferSPORT0;
	// DMA inner loop count
	*pDMA1_X_COUNT = 4;
	// Inner loop address increment
	*pDMA1_X_MODIFY = 4;
	
	
	// Set up DMA2 to transmit
	// Map DMA2 to Sport0 TX
	*pDMA2_PERIPHERAL_MAP = 0x2000;
	
	// Configure DMA2
	// 32-bit transfers, Autobuffer mode
	*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
	// Start address of data buffer
	*pDMA2_START_ADDR = (void*)g_iTxBufferSPORT0;
	// DMA inner loop count
	*pDMA2_X_COUNT = 4;
	// Inner loop address increment
	*pDMA2_X_MODIFY = 4;
}

//--------------------------------------------------------------------------//
// Function:	Enable_DMA_Sport											//
//																			//
// Description:	Enable DMA1, DMA2, Sport0 TX and Sport0 RX					//
//--------------------------------------------------------------------------//
void Enable_Sport0_DMA(void)
{
	// enable DMAs
	*pDMA2_CONFIG	= (*pDMA2_CONFIG | DMAEN);
	*pDMA1_CONFIG	= (*pDMA1_CONFIG | DMAEN);
	
	// enable Sport0 TX and RX
	*pSPORT0_TCR1 	= (*pSPORT0_TCR1 | TSPEN);
	*pSPORT0_RCR1 	= (*pSPORT0_RCR1 | RSPEN);
}

//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Description:	Initialize Interrupt for Sport0 RX							//
//--------------------------------------------------------------------------//
void Init_Sport0_Interrupts(void)
{
	// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9 
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xffffff2f;
	*pSIC_IAR2 = 0xffffffff;

	// assign ISRs to interrupt vectors
	// Sport0 RX ISR -> IVG 9
	register_handler(ik_ivg9, Sport0_RX_ISR);

	// enable Sport0 RX interrupt
	*pSIC_IMASK = 0x00000200;
}


//--------------------------------------------------------------------------//
// Function:	Sport0_RX_ISR												//
//																			//
// Description: This ISR is executed after a complete frame of input data 	//
//				has been received. The new samples are stored in 			//
//				g_lAudioInputBufferL and g_lAudioInputBufferR		 		//
//				respectively.  New data is pulled from the pregenerated 
//				sin table g_lAudioOutputBufferRef and put in the dma 		//
//				transmit buffer.											//
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(Sport0_RX_ISR)
{
	// confirm interrupt handling
	*pDMA1_IRQ_STATUS = 0x0001;
	
	if( g_ucAudioInEnable )
	{
		g_iSampleIndex++;
		// audio buffer size, devided by the number of samples required for a full sinewave
		if( g_iSampleIndex > g_iBufferSampleSize )
		{
			g_iSampleIndex = 0;
		}

		// copy input data from dma input buffer into variables
		g_lAudioInputBufferL[g_iSampleIndex] = (g_iRxBufferSPORT0[INTERNAL_SPDIF_RX_L0] * 0x100);
		g_lAudioInputBufferR[g_iSampleIndex] = (g_iRxBufferSPORT0[INTERNAL_SPDIF_RX_R0] * 0x100);

		long lOut;
		lOut = g_lAudioOutputBufferRef[g_uiOutputSampleIndex];
		g_uiOutputSampleIndex++;
		if( g_uiOutputSampleIndex == (int)(g_fSamplesPerSin) )
		{
			g_uiOutputSampleIndex = 0;
		}

		
		// set the channel that is of interest
		g_iTxBufferSPORT0[INTERNAL_SPDIF_TX_L0] = lOut;
		g_iTxBufferSPORT0[INTERNAL_SPDIF_TX_R0] = lOut;

		g_lSampleCount++;
	}
	else
	{
		g_uiOutputSampleIndex = 0;
	}
}