ad1938_test.h

ADSP 地层驱动

/*********************************************************************************

Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved. 

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.  


Description:
			This is the source code for the Blackfin EZ-Audio Power On Self Test 
			(POST).
			
*********************************************************************************/
#ifndef _AD1938_TEST_H_
#define _AD1938_TEST_H_

#include <sys\exception.h>
#include <cdefBF533.h>
#include <ccblkfn.h>
#include <sysreg.h>
#include "bitDefs.h"



#define SAMPLE_RATE 48
#define TDM_SLOTS 16

#define DAC_SAMPLE_RATE	DAC_SR_48K
#define ADC_SAMPLE_RATE	ADC_SR_48K


#define INPUT_MUL 	INPUT512 
#define DAC_FMT 	DAC_FMT_TDM

#define DMA_CHANNELS	32
#define DAC_CHANNELS	DAC_CHANNELS_16
#define ADC_CHANNELS	ADC_CHANNELS_16
#define MC_WSIZE		0x1000

// names for slots in ad1938 audio frame
#define INTERNAL_ADC_L1		0
#define INTERNAL_ADC_R1		2
#define INTERNAL_ADC_L2		4
#define INTERNAL_ADC_R2		6
#define INTERNAL_ADC_L3		1
#define INTERNAL_ADC_R3		3
#define INTERNAL_ADC_L4		5
#define INTERNAL_ADC_R4		7


#define INTERNAL_DAC_L1			16
#define INTERNAL_DAC_R1			18
#define INTERNAL_DAC_L2			20
#define INTERNAL_DAC_R2			22
#define INTERNAL_DAC_L3			24
#define INTERNAL_DAC_R3			26
#define INTERNAL_DAC_L4			28
#define INTERNAL_DAC_R4			30
#define INTERNAL_DAC_L5			17
#define INTERNAL_DAC_R5			19
#define INTERNAL_DAC_L6			21
#define INTERNAL_DAC_R6			23
#define INTERNAL_DAC_L7			25
#define INTERNAL_DAC_R7			27
#define INTERNAL_DAC_L8			29
#define INTERNAL_DAC_R8			31



// SPORT0 word length
#define SLEN_32	0x001f
#define SLEN_24	0x0017


// DMA flow mode
#define FLOW_1	0x1000

//--------------------------------------------------------------------------//
// Global variables															//
//--------------------------------------------------------------------------//
extern volatile long 			g_lADC_TestChannel;
extern volatile long 			g_lDAC_TestChannel;


//--------------------------------------------------------------------------//
// Prototypes																//
//--------------------------------------------------------------------------//
void Init1938_A(void);
void Init1938_B(void);

void Init_Sport1(void);
void Init_Sport1_DMA(void);
void Init_Sport1_Interrupts(void);
void Enable_Sport1_DMA(void);



// in file ISRs.c
EX_INTERRUPT_HANDLER(Sport1_RX_ISR);


// names for codec registers, used for iCodec1938TxRegs[]
#define PLL_CLK_CONTROL_0	0x0000
#define PLL_CLK_CONTROL_1	0x0001
#define DAC_CONTROL_0		0x0002
#define DAC_CONTROL_1		0x0003
#define DAC_CONTROL_2		0x0004
#define DAC_MUTE_REG		0x0005
#define DAC_VOLUME_1L		0x0006
#define DAC_VOLUME_1R		0x0007
#define DAC_VOLUME_2L		0x0008
#define DAC_VOLUME_2R		0x0009
#define DAC_VOLUME_3L		0x000a
#define DAC_VOLUME_3R		0x000b
#define DAC_VOLUME_4L		0x000c
#define DAC_VOLUME_4R		0x000d
#define ADC_CONTROL_0		0x000e
#define ADC_CONTROL_1		0x000f
#define ADC_CONTROL_2		0x0010

//PLL_CLK_CONTROL_0
#define DIS_ADC_DAC			(b7_0)
#define ENA_ADC_DAC			(b7_1)

#define PLL_IN_MCLK			(b6_0 | b5_0)
#define PLL_IN_DLRCLK		(b6_0 | b5_1)
#define PLL_IN_ALRCLK		(b6_1 | b5_0)

#define MCLK_OUT_XTAL		(b4_0 | b3_0)
#define MCLK_OUT_256FS		(b4_0 | b3_1)
#define MCLK_OUT_512FS		(b4_1 | b3_0)
#define MCLK_OUT_OFF		(b4_1 | b3_1)

#define INPUT256			(b2_0 | b1_0)
#define INPUT284			(b2_0 | b1_1)
#define INPUT512			(b2_1 | b1_0)
#define INPUT768			(b2_1 | b1_1)

#define PLL_PWR_UP			(b0_0)
#define PLL_PWR_DWN			(b0_1)


//PLL_CLK_CONTROL_1
#define DIS_VREF			(b2_0)
#define ENA_VREF			(b2_1)

#define ADC_CLK_PLL			(b1_0)
#define ADC_CLK_MCLK		(b1_1)

#define DAC_CLK_PLL			(b0_0)
#define DAC_CLK_MCLK		(b0_1)


//DAC_CONTROL_0
#define DAC_FMT_I2S			(b7_0 | b6_0)
#define DAC_FMT_TDM			(b7_0 | b6_1)
#define DAC_FMT_AUX			(b7_1 | b6_0)
#define DAC_FMT_DUALTDM		(b7_1 | b6_1)


#define DAC_BLK_DLY_1		(b5_0 | b4_0 | b3_0)
#define DAC_BLK_DLY_0		(b5_0 | b4_0 | b3_1)
#define DAC_BLK_DLY_8		(b5_0 | b4_1 | b3_0)
#define DAC_BLK_DLY_12		(b5_0 | b4_1 | b3_1)
#define DAC_BLK_DLY_16		(b5_1 | b4_0 | b3_0)

#define DAC_SR_48K			(b2_0 | b1_0)
#define DAC_SR_96K			(b2_0 | b1_1)
#define DAC_SR_192K			(b2_1 | b1_0)

#define DAC_PWR_UP			(b0_0)
#define DAC_PWR_DWN			(b0_1)


//DAC_CONTROL_1
#define DAC_BCLK_POL_NORM		(b7_0)
#define DAC_BCLK_POL_INV		(b7_1)

#define DAC_BCLK_SRC_PIN		(b6_0)
#define DAC_BCLK_SRC_INTERNAL	(b6_1)

#define DAC_BCLK_SLAVE			(b5_0)
#define DAC_BCLK_MASTER			(b5_1)

#define DAC_LRCLK_SLAVE			(b4_0)
#define DAC_LRCLK_MASTER		(b4_1)

#define DAC_LRCLK_POL_NORM		(b3_0)
#define DAC_LRCLK_POL_INV		(b3_1)

#define DAC_CHANNELS_2			(b2_0 | b1_0)
#define DAC_CHANNELS_4			(b2_0 | b1_1)
#define DAC_CHANNELS_8			(b2_1 | b1_0)
#define DAC_CHANNELS_16			(b2_1 | b1_1)

#define DAC_LTCH_MID			(b0_0)
#define DAC_LTCH_END			(b0_1)


//DAC_CONTROL_2
#define DAC_OUT_POL_NORM	(b5_0)
#define DAC_OUT_POL_INV		(b5_1)

#define DAC_WIDTH_24		(b4_0 | b3_0)
#define DAC_WIDTH_20		(b4_0 | b3_1)
#define DAC_WIDTH_16		(b4_1 | b3_1)

#define DAC_DEEMPH_FLAT		(b2_0 | b1_0)
#define DAC_DEEMPH_48K		(b2_0 | b1_1)
#define DAC_DEEMPH_44_1K	(b2_1 | b1_0)
#define DAC_DEEMPH_32K		(b2_1 | b1_1)

#define DAC_UNMUTE			(b0_0)
#define DAC_MUTE			(b0_1)


//ADC_CONTROL_0
#define ADC_SR_48K			(b7_0 | b6_0)
#define ADC_SR_96K			(b7_0 | b6_1)
#define ADC_SR_192K			(b7_1 | b6_0)

#define ADC_R2_UNMUTE		(b5_0)
#define ADC_R2_MUTE			(b5_1)

#define ADC_L2_UNMUTE		(b4_0)
#define ADC_L2_MUTE			(b4_1)

#define ADC_R1_UNMUTE		(b3_0)
#define ADC_R1_MUTE			(b3_1)

#define ADC_L1_UNMUTE		(b2_0)
#define ADC_L1_MUTE			(b2_1)

#define ADC_HP_FILT_OFF		(b1_0)
#define ADC_HP_FILT_ON		(b1_1)

#define ADC_PWR_UP			(b0_0)
#define ADC_PWN_DWN			(b0_1)


//ADC_CONTROL_1		0x000f
#define ADC_LTCH_MID		(b7_0)
#define ADC_LTCH_END		(b7_1)

#define ADC_FMT_I2S			(b6_0 | b5_0)
#define ADC_FMT_TDM			(b6_0 | b5_1)
#define ADC_FMT_AUX			(b6_1 | b5_0)

#define ADC_BLK_DLY_1		(b4_0 | b3_0 | b2_0)
#define ADC_BLK_DLY_0		(b4_0 | b3_0 | b2_1)
#define ADC_BLK_DLY_8		(b4_0 | b3_1 | b2_0)
#define ADC_BLK_DLY_12		(b4_0 | b3_1 | b2_1)
#define ADC_BLK_DLY_16		(b4_1 | b3_0 | b2_0)

#define ADC_WIDTH_24		(b1_0 | b0_0)
#define ADC_WIDTH_20		(b1_0 | b0_1)
#define ADC_WIDTH_16		(b1_1 | b0_1)


//ADC_CONTROL_2		0x0010
#define ADC_BCLK_SRC_PIN		(b7_0)
#define ADC_BCLK_SRC_INTERNAL	(b7_1)

#define ADC_BCLK_SLAVE			(b6_0)
#define ADC_BCLK_MASTER			(b6_1)

#define ADC_CHANNELS_2			(b5_0 | b4_0)
#define ADC_CHANNELS_4			(b5_0 | b4_1)
#define ADC_CHANNELS_8			(b5_1 | b4_0)
#define ADC_CHANNELS_16			(b5_1 | b4_1)

#define ADC_LRCLK_SLAVE			(b3_0)
#define ADC_LRCLK_MASTER		(b3_1)

#define ADC_LRCLK_POL_NORM		(b2_0)
#define ADC_LRCLK_POL_INV		(b2_1)

#define ADC_BCLK_POL_NORM		(b1_0)
#define ADC_BCLK_POL_INV		(b1_1)

#define ADC_LRCLK_FMT_50_50		(b0_0)
#define ADC_LRCLK_FMT_PULSE		(b0_1)

#endif //#ifndef _AD1938_TEST_H_