ad1938_test.c

ADSP 地层驱动

/*****************************************************************************
**																			**
**	 Name: 	AD1938_Test.c											        **	
**																			**
******************************************************************************
*********************************************************************************

Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved. 

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.  


Description:
			This is the source code for the Blackfin EZ-Audio Power On Self Test 
			(POST).
			
*********************************************************************************/
#include <stdio.h>
#include <math.h>
#include <filter.h>
#include "Test_EZ_Audio.h"
#include "AD1938_Test.h"



//////////////////////////////////////////////////////////////////////////////
// 							Common defines
//////////////////////////////////////////////////////////////////////////////



//////////////////////////////////////////////////////////////////////////////
// 							Globals
//////////////////////////////////////////////////////////////////////////////
volatile long 			g_lADC_TestChannel = INTERNAL_ADC_L1;
volatile long 			g_lDAC_TestChannel = INTERNAL_DAC_L1;
volatile long 			g_lRxBufferSPORT1[DMA_CHANNELS];
volatile long 			g_lTxBufferSPORT1[DMA_CHANNELS];





//--------------------------------------------------------------------------//
// Function:	Sport1_RX_ISR												//
//																			//
// Description: This ISR is executed after a complete frame of input data 	//
//				has been received. The new samples are stored in 			//
//				g_lAudioInputBufferL and g_lAudioInputBufferR		 		//
//				respectively.  New data is pulled from the pregenerated 
//				sin table g_lAudioOutputBufferRef and put in the dma 		//
//				transmit buffer.											//
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(Sport1_RX_ISR)
{
	// confirm interrupt handling
	*pDMA3_IRQ_STATUS = 0x0001;
	
	if( g_ucAudioInEnable )
	{
		g_iSampleIndex++;
		// audio buffer size, devided by the number of samples required for a full sinewave
		if( g_iSampleIndex > g_iBufferSampleSize )
		{
			g_iSampleIndex = 0;
		}

		g_lAudioInputBufferL[g_iSampleIndex] = (g_lRxBufferSPORT1[g_lADC_TestChannel]);
		g_lAudioInputBufferR[g_iSampleIndex] = (g_lRxBufferSPORT1[g_lADC_TestChannel+2]);

		long lOut;
		lOut = g_lAudioOutputBufferRef[g_uiOutputSampleIndex];
		g_uiOutputSampleIndex++;
		if( g_uiOutputSampleIndex == (int)(g_fSamplesPerSin) )
		{
			g_uiOutputSampleIndex = 0;
		}

		// zerof all the channels
		g_lTxBufferSPORT1[INTERNAL_DAC_L1] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R1] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L2] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R2] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L3] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R3] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L4] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R4] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L5] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R5] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L6] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R6] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L7] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R7] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_L8] = 0;
		g_lTxBufferSPORT1[INTERNAL_DAC_R8] = 0;
		
		// set the channel that is of interest
		g_lTxBufferSPORT1[g_lDAC_TestChannel] = lOut;
		g_lTxBufferSPORT1[g_lDAC_TestChannel+2] = lOut;

		g_lSampleCount++;
	}
	else
	{
		g_uiOutputSampleIndex = 0;
	}
}




//--------------------------------------------------------------------------//
// Function:	void Init1938_A(void)										//
//																			//
// Description:  Configure the 1938 ADC/DAC
//
//--------------------------------------------------------------------------//
void Init1938_A(void)
{
	int i, j;

	const short sCodec1938_ATxRegs[] =
	{	0x8,		 
		PLL_CLK_CONTROL_0,	(DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF  | INPUT_MUL | PLL_PWR_DWN ), 0x8,
		PLL_CLK_CONTROL_1,	(DAC_CLK_PLL | ADC_CLK_PLL | ENA_VREF ), 0x8,
		DAC_CONTROL_0,		(DAC_FMT | DAC_BLK_DLY_1 | DAC_SAMPLE_RATE | DAC_PWR_UP), 0x8,
		DAC_CONTROL_1,		(DAC_BCLK_POL_INV | DAC_BCLK_SRC_PIN | DAC_BCLK_SLAVE | DAC_LRCLK_SLAVE | DAC_LRCLK_POL_NORM | DAC_CHANNELS | DAC_LTCH_MID), 0x8,
		DAC_CONTROL_2,		(DAC_OUT_POL_NORM | DAC_WIDTH_24 | DAC_DEEMPH_FLAT | DAC_UNMUTE), 0x8,
		ADC_CONTROL_0,		(ADC_SAMPLE_RATE |  ADC_R2_UNMUTE | ADC_L2_UNMUTE | ADC_R1_UNMUTE | ADC_L1_UNMUTE |ADC_HP_FILT_OFF | ADC_PWR_UP), 0x8, 	
		ADC_CONTROL_1,		(ADC_LTCH_MID | ADC_FMT_AUX | ADC_BLK_DLY_1 | ADC_WIDTH_24), 0x8,
		ADC_CONTROL_2,		(ADC_BCLK_SRC_PIN | ADC_BCLK_MASTER | ADC_CHANNELS | ADC_LRCLK_MASTER | ADC_LRCLK_POL_INV | ADC_BCLK_POL_INV | ADC_LRCLK_FMT_PULSE), 0x8,
		DAC_MUTE_REG,		0x00,	0x8,
		DAC_VOLUME_1L,		0x00,	0x8,
		DAC_VOLUME_1R,		0x00,	0x8,
		DAC_VOLUME_2L,		0x00,	0x8,
		DAC_VOLUME_2R,		0x00,	0x8,
		DAC_VOLUME_3L,		0x00,	0x8,
		DAC_VOLUME_3R,		0x00,	0x8,
		DAC_VOLUME_4L,		0x00,	0x8,
		DAC_VOLUME_4R,		0x00,	0x8,
		PLL_CLK_CONTROL_0,	(DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT_MUL | PLL_PWR_UP ),	0x8,
		PLL_CLK_CONTROL_0,	(ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT_MUL | PLL_PWR_UP )
	};
	
	

	*pSPI_BAUD = 16;
	for (i = 0; i < sizeof(sCodec1938_ATxRegs)/sizeof(short); i= i+3)
	{
		*pDMA5_CONFIG = WDSIZE_8;
		*pDMA5_X_COUNT = 3;
		*pDMA5_X_MODIFY = 2;
		*pDMA5_START_ADDR = (void*)&sCodec1938_ATxRegs[i];
		*pSPI_CTL = TIMOD_DMA_TX |  MSTR;
		*pDMA5_PERIPHERAL_MAP	= 0x5000;
		*pFIO_FLAG_C	= 0x0001; // select codec A
		*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
		*pSPI_CTL = (*pSPI_CTL | SPE);
		// wait until dma transfers for spi are finished 
		for (j=0; j<0xaff0; j++) asm("nop;");
		*pSPI_CTL = 0x0000;
		*pFIO_FLAG_S	= 0x0001;
	}
	
	// unconfigur DMA5
	*pDMA5_CONFIG = 0;
	*pDMA5_START_ADDR = 0;
	*pDMA5_X_COUNT = 0;
	*pDMA5_X_MODIFY = 0;
}

//--------------------------------------------------------------------------//
// Function:	void Init1938_B(void)										//
//																			//
// Description:  Configure the 1938 ADC/DAC
//
//--------------------------------------------------------------------------//
void Init1938_B(void)
{
	int i, j;

	const short sCodec1938_BTxRegs[] =
	{	0x8,	
		PLL_CLK_CONTROL_0,	(DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT_MUL | PLL_PWR_DWN ), 0x8,
		PLL_CLK_CONTROL_1,	(DAC_CLK_PLL | ADC_CLK_PLL | ENA_VREF ),0x8,
		DAC_CONTROL_0,		(DAC_FMT | DAC_BLK_DLY_1 | DAC_SAMPLE_RATE | DAC_PWR_UP),0x8,
		DAC_CONTROL_1,		(DAC_BCLK_POL_INV | DAC_BCLK_SRC_PIN | DAC_BCLK_SLAVE | DAC_LRCLK_SLAVE | DAC_LRCLK_POL_NORM | DAC_CHANNELS | DAC_LTCH_MID),0x8,
		DAC_CONTROL_2,		(DAC_OUT_POL_NORM | DAC_WIDTH_24 | DAC_DEEMPH_FLAT | DAC_UNMUTE),0x8,
		ADC_CONTROL_0,		(ADC_SAMPLE_RATE |  ADC_R2_UNMUTE | ADC_L2_UNMUTE | ADC_R1_UNMUTE | ADC_L1_UNMUTE |ADC_HP_FILT_OFF | ADC_PWR_UP), 0x8,
		ADC_CONTROL_1,		(ADC_LTCH_MID | ADC_FMT_AUX | ADC_BLK_DLY_1 | ADC_WIDTH_24),0x8,
		ADC_CONTROL_2,		(ADC_BCLK_SRC_PIN | ADC_BCLK_SLAVE | ADC_CHANNELS | ADC_LRCLK_SLAVE | ADC_LRCLK_POL_INV | ADC_BCLK_POL_INV| ADC_LRCLK_FMT_PULSE),0x8,
		DAC_MUTE_REG,		0x00,0x8,
		DAC_VOLUME_1L,		0x00,0x8,
		DAC_VOLUME_1R,		0x00,0x8,
		DAC_VOLUME_2L,		0x00,0x8,
		DAC_VOLUME_2R,		0x00,0x8,
		DAC_VOLUME_3L,		0x00,0x8,
		DAC_VOLUME_3R,		0x00,0x8,
		DAC_VOLUME_4L,		0x00,0x8,
		DAC_VOLUME_4R,		0x00,0x8,
		PLL_CLK_CONTROL_0,	(DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT_MUL | PLL_PWR_UP ),0x8,
		PLL_CLK_CONTROL_0,	(ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT_MUL | PLL_PWR_UP )
	};

	*pSPI_BAUD = 16;
	for (i = 0; i < sizeof(sCodec1938_BTxRegs)/sizeof(short); i= i+3)
	{

		*pSPI_CTL = TIMOD_DMA_TX |  MSTR; //SIZE |;
		*pDMA5_PERIPHERAL_MAP	= 0x5000;
		*pDMA5_CONFIG = WDSIZE_8;
		*pDMA5_X_COUNT = 3;
		*pDMA5_X_MODIFY = 2;
		*pDMA5_START_ADDR = (void*)&sCodec1938_BTxRegs[i];
		*pFIO_FLAG_C	= 0x0002;	// SELECT codec B
		*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
		*pSPI_CTL = (*pSPI_CTL | SPE);
		// wait until dma transfers for spi are finished 
		for (j=0; j<0xaff0; j++) asm("nop;");
		*pSPI_CTL = 0x0000;
		*pFIO_FLAG_S	= 0x0002;
	}
	
	// unconfigur DMA5
	*pDMA5_CONFIG = 0;
	*pDMA5_START_ADDR = 0;
	*pDMA5_X_COUNT = 0;
	*pDMA5_X_MODIFY = 0;
}


//--------------------------------------------------------------------------//
// Function:	void Init_Sport1(void)										//
//																			//
// Description:  Setup SPORT1 for the 1938 adc/dac
//
//--------------------------------------------------------------------------//
void Init_Sport1(void)
{
	// Sport1 receive configuration
	// External CLK, External Frame sync, MSB first
	// 32-bit data
	*pSPORT1_RCR1 = RFSR;
	*pSPORT1_RCR2 = SLEN_32|RXSE;
	
	// Sport1 transmit configuration
	// External CLK, External Frame sync, MSB first
	// 24-bit data
	*pSPORT1_TCR1 = TFSR;
	*pSPORT1_TCR2 = SLEN_32|TXSE;
	
	// Enable MCM 8 transmit & receive channels
	*pSPORT1_MTCS0 = 0x0000FFFF;
	*pSPORT1_MRCS0 = 0x0000FFFF;
	
	// Set MCM configuration register and enable MCM mode
	*pSPORT1_MCMC1 = 0x0000 | MC_WSIZE;
	*pSPORT1_MCMC2 = 0x101C;
}

//--------------------------------------------------------------------------//
// Function:	void Init_Sport1_DMA(void)									//
//																			//
// Description:  Setup SPORT1 dma to/from 1938 adc/dac
//
//--------------------------------------------------------------------------//
void Init_Sport1_DMA(void)
{
	// Set up DMA3 to receive
	// Map DMA3 to Sport1 RX
	*pDMA3_PERIPHERAL_MAP = 0x3000;
	
	// Configure DMA3
	// 32-bit transfers, Interrupt on completion, Autobuffer mode
	*pDMA3_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
	// Start address of data buffer
	*pDMA3_START_ADDR = (void*)g_lRxBufferSPORT1;
	// DMA inner loop count
	*pDMA3_X_COUNT = DMA_CHANNELS ;
	// Inner loop address increment
	*pDMA3_X_MODIFY	= 4;
	
	
	// Set up DMA4 to transmit
	// Map DMA4 to Sport1 TX
	*pDMA4_PERIPHERAL_MAP = 0x4000;
	
	// Configure DMA4
	// 32-bit transfers, Autobuffer mode
	*pDMA4_CONFIG = WDSIZE_32 | FLOW_1;
	// Start address of data buffer
	*pDMA4_START_ADDR = (void*)g_lTxBufferSPORT1;
	// DMA inner loop count
	*pDMA4_X_COUNT = DMA_CHANNELS ;
	// Inner loop address increment
	*pDMA4_X_MODIFY	= 4;
}



//--------------------------------------------------------------------------//
// Function:	void Init_Sport1_Interrupts(void)							//
//																			//
// Description:  Setup SPORT1 interrupts to/from 1938 adc/dac
//
//--------------------------------------------------------------------------//
void Init_Sport1_Interrupts(void)
{
	// Set Sport1 RX (DMA3) interrupt priority to 2 = IVG9 
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xffff2fff;
	*pSIC_IAR2 = 0xffffffff;

	// assign ISRs to interrupt vectors
	// Sport1 RX ISR -> IVG 9
	register_handler(ik_ivg9, Sport1_RX_ISR);		

	// enable Sport1 RX interrupt
	*pSIC_IMASK = 0x00000800;
	ssync();
}



//--------------------------------------------------------------------------//
// Function:	void Enable_Sport1_DMA(void)	 							//
//																			//
// Description:  turn on  SPORT1 dma to/from 1938 adc/dac
//
//--------------------------------------------------------------------------//
void Enable_Sport1_DMA(void)
{
	// enable DMAs
	*pDMA4_CONFIG	= (*pDMA4_CONFIG | DMAEN);
	*pDMA3_CONFIG	= (*pDMA3_CONFIG | DMAEN);
	
	// enable Sport1 TX and RX
	*pSPORT1_TCR1 	= (*pSPORT1_TCR1 | TSPEN);
	*pSPORT1_RCR1 	= (*pSPORT1_RCR1 | RSPEN);
}