pll.c

ADSP 地层驱动

/******************************************************************************/
//
// Name: 	BF533 EZ-KIT PLL Setup
//
/******************************************************************************

(C) Copyright 2005 - Analog Devices, Inc.  All rights reserved.

File Name:		PLL.c

Date Modified:	10/25/04		Rev 0.2

Software:       VisualDSP++4.5

Hardware:		ADSP-BF533 EZ-KIT Board

Special Connections:  None

Purpose:		The file sets up the PPI transfer
				
				

*********************************************************************************/


#include <cdefBF533.h>
#include <ccblkfn.h>
#include <sysreg.h>


//--------------------------------------------------------------------------//
// Function:	void Init_PLL(void)
//																			//
// Description: setup pll
//	 			CLKIN on BF533 EZ-KIT is 27 MHz
// 				MAX CCLK for BF533 is either 500, 600 or 756 MHz depending on version
// 				MAX SCLK for BF533 is 133 MHz
//
//--------------------------------------------------------------------------//
void Init_PLL(void)
{
	volatile int test=0;

	sysreg_write(reg_SYSCFG, 0x32);		//Initialize System Configuration Register

	*pSIC_IWR = 0x1;
	
	*pPLL_CTL = 0x2C00;		// MSEL is 22, which gives:	VCO of 594 MHz (27*22=594)

	*pPLL_DIV = 0x5;		// SSEL is 5, which gives:	SCLK of 118.8 MHz (594/5=118.8)
							// CSEL is 0, which gives:	CCLK of 594 MHz (594/1=594)	
	ssync();
	idle();
	


}//end Init_PLL