📄 boot.s
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IF (:DEF: ZR4050)
; Load the SPLL Control Register
LDR r0, =SPLLCTR
LDR r1, =0x00014F42
STR r1, [r0]
; Check for SPLL Lock
SpllLock
LDR r0, =SPLLCTR
LDR r1, [r0]
TST r1, #0x00020000
BEQ SpllLock
; Pause for 1.4mSec to let the SPLL stabilize
LDR r0, =0x10000
spll_pause_loop
SUBS r0, r0, #1
BNE spll_pause_loop
ENDIF
SDRAMsetup
;-------------------------------------------------------------
; FIRE SDRAM setup
;-------------------------------------------------------------
LDR r0, =SDRAM132 ; use 128M16 memories
LDR r1, =SDCONF
STR r0, [r1]
LDR r0, =PRECMD ; precharge all banks
LDR r1, =SDMODE
STR r0, [r1]
LDR r0, =RFSHCMD ; force 2 auto refresh cycles
STR r0, [r1]
STR r0, [r1]
LDR r0, =LMODECMD ; load SDRAM mode register
STR r0, [r1]
LDR r0, =SDRAM132R ; enable refresh
LDR r1, =SDCONF
STR r0, [r1]
; LDR r0, =XFEREN ; enable data transfers
; LDR r1, =SDARB
; STR r0, [r1]
;-------------------------------------------------------------
; FIRE System Bus setup
; Enable CS0 & CS1 (Flash), CS2 (FAX), and CS3 (UI)
;-------------------------------------------------------------
LDR r0, =SBSETUP
LDR r1, =SBSEL0 ; setup CS0 configuration register
STR r0, [r1]
LDR r0, =SBSETUP ; 0x1FFF0700 ; Use MAX values for the CPLD stuff
LDR r1, =SBSEL1 ; setup CS1 configuration register
STR r0, [r1]
LDR r0, =SBSETUP
LDR r1, =SBSEL2 ; setup CS2 configuration register
STR r0, [r1]
IF (:DEF: ZR4050)
; The current SBSETUP setup values are:
;
; 0x04080700 which is
;
; AM:0 auto-ack mode
; SP:0 Read/Write Strobe Polarity active LOW
; BB:0 Back-to-back Enable not used
; BM:0 Burst Mode not used
; AS:7 Acknowledge Delay, Auto-ack after 8 cycles
; RH:0 Read Strobe Hold Interval, 0 clks between
; read de-assertion and select
; WH:1 Write Strobe Hold Interval, 1 SystemBus
; clock cycles between write strobe
; deassertion and select assertion
; SUP:0 Read/Write Strobe Setup Interval,
; 0 SystemBus clock cycles between select
; assertion and read/write strobe assertion
; DS:1 DeSelect Interval, After deassertion of
; SBCS the same or another select is asserted after
; (DS+1) SystemBus clock cycles only
; (see also field BB).
; DE:0 Device Endian Mode same as ARM
; DW:0 Device Data Width 8 bit device, connected
; to SBD[7:0]. Asserted address is SBA[21:0]
; (byte address)
;
; For 4050 which has UI problems, try setting
; RH, WH, SUP, and DS to the max values
; which is 0x1FFF0700
;
; NOTE: This helps some, but doesn't fix the problem.
;
;
LDR r0, =0x1FFF0700
ENDIF
LDR r0, =SBSETUP ; 0x1FFF0700
LDR r1, =SBSEL3 ; setup CS3 configuration register
STR r0, [r1]
LDR r0, =SBEN0123 ; setup system bus configuration register
LDR r1, =SBCONF
STR r0, [r1]
;----------------------------------------------------------------------------
; Enable caches to speed up execution
;----------------------------------------------------------------------------
BL InvalidateInstrCache
BL InvalidateDataCache
BL InstrCacheEnable
BL DataCacheEnable
;; Enable Tightly Coupled Memory (TCM)
ldr r1,=TCMC
mov r0,#TCMBASE
orr r0,r0,#1
str r0,[r1]
ldr r1,=TCMBASE
ldr r0,=0x12340001
str r0,[r1,#4]
IF (:LNOT: :DEF: DISABLE_FAST_BOOT)
;;; Determine if RESET was initiated by a Programmed RESET
ldr r0,=RESCTR
ldr r0,[r0,#0]
tst r0,#0x200000 ;Check Bit 21
beq NormalBoot ;Was it a Programmed RESET?
ldr r3,=0x12340002
str r3,[r1,#4]
ldr r0,[r1,#0] ;Yes.Check TCM power flag
ldr r2,=0x12345678
cmp r0,r2
bne NormalBoot ;Was it a power button RESET?
str r3,[r1,#0] ;Yes. Wipe out code for later test
ldr r0, Load_RO_Start ; Start of the code in Flash
ldr r1, Exec_RO_Start ; Start of the code in SDRAM
ldr r2, =FIRMWARE_START-4 ; Start of application firmware
mov r3, #0x20000000
add r1, r1, r3
add r2, r2, r3
1
cmp r1, r2 ; Check to set flags
ldrcc r3, [r0], #4 ; Get value from ROM
strcc r3, [r1], #4 ; Put value in RAM
bcc %b1 ; Continue
ldr r0,=0x12345678 ; Set flag showing fast restart processed
ldr r1,=TCMBASE
str r0,[r1,#4]
ldr r0, =ARMCTR ;Clear the address translation bits
ldr r1, [r0] ;to execute out of SDRAM
bic r1, r1, #ATRANSBITS
str r1, [r0]
IF (:LNOT: :DEF: ZR4050)
LDR r0, =SIFCFST ;Clear the SPI FIFO Cache Mode
ELSE
LDR r0, =SPICFST ;Clear the SPI FIFO Cache Mode
ENDIF
LDR r1, [r0]
BIC r1, r1, #CMODEBIT
STR r1, [r0]
IF {TRUE}
;; Last test. Verify code checksum
;; TCM[2] = the code size in bytes
;; TCM[3] = the saved code checksum
ldr r12,=TCMBASE
ldr r5,[r12,#8] ;Get code size
ldr r2,=FIRMWARE_START
mov r1,#0
mov r0,#0
0 ;; Accumulate the code checksum
cmp r0,r5
ldrcc r3,[r2],#4
addcc r0,r0,#4
addcc r1,r3,r1
bcc %b0
ldr r0,[r12,#0xc] ;Get the saved checksum
cmp r0,r1
bne AbortFastBoot ;Abort if not equal
ENDIF
ldr r0,=FIRMWARE_START ;restart firmware in RAM
mov pc,r0
; Checksum of code failed (should be a rare case).
; The only safe thing to do is RESET the processor and allow it to
; re-read the ROM contents.
AbortFastBoot
ldr r0, =RESCTR
ldr r1, =1
str r1, [r0]
StallHere ;Just a sanity check.
b StallHere ;Should never get here!
ENDIF ; DISABLE_FAST_BOOT
;----------------------------------------------------------------------------
; Move (if necessary) vector table, code, & RW data from ROM to RAM.
; ZI data cleared in init.s
;----------------------------------------------------------------------------
; don't copy anything if address translation bits not set (already done)
NormalBoot
LDR r1, =ARMCTR
LDR r0, [r1]
MOV r2, #ATRANSBITS
TST r0, r2
BEQ SetupOverlay
; move vector table
LDR a1, Load_V_Start ; Start of the vector table in Flash
LDR a2, Exec_V_Start ; Start of the vector table in SDRAM
LDR a3, Exec_V_End ; End of the vector table in SDRAM
MOV a4, #0x20000000
ADD a2, a2, a4
ADD a3, a3, a4
V_Copy
CMP a2, a3 ; Check to set flags
LDRCC a4, [a1], #4 ; Get value from ROM
STRCC a4, [a2], #4 ; Put value in RAM
BCC V_Copy ; Continue
; move code
LDR a1, Load_RO_Start ; Start of the code in Flash
LDR a2, Exec_RO_Start ; Start of the code in SDRAM
LDR a3, Exec_RO_End ; End of the code in SDRAM
MOV a4, #0x20000000
ADD a2, a2, a4
ADD a3, a3, a4
RO_Copy
CMP a2, a3 ; Check to set flags
LDRCC a4, [a1], #4 ; Get value from ROM
STRCC a4, [a2], #4 ; Put value in RAM
BCC RO_Copy ; Continue
; move rw data
LDR a1, Load_RW_Start ; Start of the rw data in Flash
LDR a2, Exec_RW_Start ; Start of the rw data in SDRAM
LDR a3, Exec_RW_End ; End of the rw data in SDRAM
MOV a4, #0x20000000
ADD a2, a2, a4
ADD a3, a3, a4
RW_Copy
CMP a2, a3 ; Check to set flags
LDRCC a4, [a1], #4 ; Get value from ROM
STRCC a4, [a2], #4 ; Put value in RAM
BCC RW_Copy ; Continue
; clear zi data in init.s
;----------------------------------------------------------------------------
; Clear the address translation bits to execute out of SDRAM
;----------------------------------------------------------------------------
LDR r0, =ARMCTR
LDR r1, [r0]
BIC r1, r1, #ATRANSBITS
STR r1, [r0]
;----------------------------------------------------------------------------
; Clear SPI FIFO Cache Mode (no longer needed, done booting)
;----------------------------------------------------------------------------
IF (:LNOT: :DEF: ZR4050)
LDR r0, =SIFCFST
ELSE
LDR r0, =SPICFST
ENDIF
LDR r1, [r0]
BIC r1, r1, #CMODEBIT
STR r1, [r0]
;----------------------------------------------------------------------------
; Setup Overlay Registers
;----------------------------------------------------------------------------
SetupOverlay
BL SetOvlRegs
;-------------------------------------------------------------
; Switch over to CPLD control of the LEDs
; Bit3 = switch LED control to CPLD
;-------------------------------------------------------------
LDR r0, =BDCTLREG
LDR r1, =LEDENABLE
STRB r1, [r0]
;-------------------------------------------------------------
; Start High Resolution Timer 0 as a free running timer which
; counts system clocks (normally at 132 MHz)
;-------------------------------------------------------------
LDR r0,=TIM_BASE
MOV r1,#0 ;Triggered by ARM clock directly
STR r1,[r0,#0x10]
MOV r1,#1
STR r1,[r0,#0x1c] ;Stop and clear timer
MOV r1,#2
STR r1,[r0,#0x1c] ;Start it up
;-------------------------------------------------------------
; TARGET_ROM branches to INT_Initialize in init.s
;-------------------------------------------------------------
B INT_Initialize ; to high-level initialization
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* UndefInt - Undefined interrupt handler */
;/* */
;/*************************************************************************/
UndefInt
B UndefInt
END
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