mytest.sum

来自「参考周立功的basic模式的CAN通讯」· SUM 代码 · 共 112 行

***********************************************************************
                         PSDsoft Express Version 7.90
                         Summary of Design Assistant
***********************************************************************
PROJECT    : mytest                        DATE : 05/18/2006
DEVICE     : uPSD3254A                     TIME : 09:36:49
MCU/DSP    : uPSD32XX    
***********************************************************************

Initial setting for Program and Data Space:
===========================================

  Main PSD flash memory will reside in this space at power-up:      Data Space Only
  Secondary PSD flash memory will reside in this space at power-up: Program Space Only

Pin Definitions:
================

Pin          Signal                    Pin
Name         Name                      Type
------------ ------------------------- ------------
pa7          pa7                       Latched address out
pa6          pa6                       Latched address out
pa5          pa5                       Latched address out
pa4          pa4                       Latched address out
pa3          pa3                       Latched address out
pa2          pa2                       Latched address out
pa1          pa1                       Latched address out
pa0          pa0                       Latched address
pb7          cs0                       External chip select - Active-Lo
pb6          cs1                       External chip select - Active-Lo
pb5          cs2                       External chip select - Active-Lo
pb4          ma0                       Combinatorial
pb1          pb1                       Logic or address
tdo          tdo                       Dedicated JTAG - TDO
tdi          tdi                       Dedicated JTAG - TDI
tck          tck                       Dedicated JTAG - TCK
tms          tms                       Dedicated JTAG - TMS
ale          ale                       ALE output  
p3.3         Tmr1_Gate                 Int1 or Timer1 Gate
p3.2         Tmr0_Gate                 Int0 or Timer0 Gate
p3.1         TxD                       UART1 TxD   
p3.0         RxD                       UART1 RxD   
p1.5         dog                       GP I/O mode 
p1.4         led                       GP I/O mode 
p1.3         TxD2                      UART2 TxD   
p1.2         RxD2                      UART2 RxD   
p1.0         p1_0                      GP I/O mode 
a11          a11                       Address line
a10          a10                       Address line
a9           a9                        Address line
a8           a8                        Address line
ad7          a7                        Data/Address line
ad6          a6                        Data/Address line
ad5          a5                        Data/Address line
ad4          a4                        Data/Address line
ad3          a3                        Data/Address line
ad2          a2                        Data/Address line
ad1          a1                        Data/Address line
ad0          a0                        Data/Address line
_Reset_In    _Reset_In                 Reset In    
Vref         VREF                      VREF input  
_rd          _rd                       Bus control output
_psen        _psen                     Bus control output
_wr          _wr                       Bus control output
USB-         USB_minus                 USB- bus    
USB+         USB_plus                  USB+ bus    
Xtal1        Xtal1                     Xtal1       
Xtal2        Xtal2                     Xtal2       

User defined nodes:
===================

None defined

Page Register settings:
=======================

pgr0 is used for paging
pgr1 is used for paging
pgr2 is used for paging
pgr3 is not used
pgr4 is not used
pgr5 is not used
pgr6 is not used
pgr7 is not used

Equations:
==========

rs0 = ((address >= ^h0000) & (address <= ^h7EFF));
csiop = ((address >= ^h7F00) & (address <= ^h7FFF));
fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hFFFF));
fs1 = ((page == 1) & (address >= ^h8000) & (address <= ^hFFFF));
fs2 = ((page == 2) & (address >= ^h8000) & (address <= ^hFFFF));
fs3 = ((page == 3) & (address >= ^h8000) & (address <= ^hFFFF));
fs4 = ((page == 4) & (address >= ^h8000) & (address <= ^hFFFF));
fs5 = ((page == 5) & (address >= ^h8000) & (address <= ^hFFFF));
fs6 = ((page == 6) & (address >= ^h8000) & (address <= ^hFFFF));
fs7 = ((page == 7) & (address >= ^h8000) & (address <= ^hFFFF));
csboot0 = ((address >= ^h0000) & (address <= ^h1FFF));
csboot1 = ((address >= ^h2000) & (address <= ^h3FFF));
csboot2 = ((address >= ^h4000) & (address <= ^h5FFF));
csboot3 = ((address >= ^h6000) & (address <= ^h7FFF));
! cs0 = ((address >= ^h8000) & (address <= ^h8FFF) & (!_wr))
     # ((address >= ^h8000) & (address <= ^h8FFF) & (!_rd));
! cs1 = ((address >= ^h9000) & (address <= ^h9FFF) & (!_wr))
     # ((address >= ^h9000) & (address <= ^h9FFF) & (!_rd));
! cs2 = ((address >= ^hA000) & (address <= ^hAFFF));
ma0 = pa0;
pa0.le = ale; "latched by ale