spkintr2.s

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////
//////// SpkIntr2.s (input unsigned 16-bit stereo, output unsigned 15bit stereo)
////////
////////	1998 Oct. 29	H.Matsuoka	Ver.0.1
////////	1999 Mar.  9	H.Matsuoka	Ver.0.2
////////	1999 Aug. 24	H.Matsuoka	Ver.0.3  PCM15
////////	1999 Oct. 14	H.Matsuoka	Ver.0.4  PCM15 stereo
////////	1999 Nov. 16	H.Matsuoka	Data unsigned 16bit
////////	2003 Dec. 03	CH.Yoon 	Ver.0.5    port to GNU33
////////

#include  "slcomm.def"
#include  "slintr.def"

#define COMPARE_A16_1			0x00048188
#define COMPARE_A16_2			0x00048190-0x00048188
#define COMPARE_A16_3			0x00048198-0x00048190
#define COMPARE_A16_4			0x000481a0-0x00048198

#define TIMER16_ODD_UNDERFLOW	0x40
#define TIMER16_5_IFLAG 		0x00040284	// 16bit Timer 5 trigar

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////// Global Symbols
//////
		.global SpkIntr2

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////// SpkIntr 
//////
SpkIntr2:
		pushn	%r4

		xld.w	%r0,SPK_DATA_0		// SPK_DATA_#

		ld.w	%r2,[%r0]			// Read HEAD
		xld.w	%r3,TIMER16_ODD_UNDERFLOW
		xld.w	%r1,TIMER16_5_IFLAG // Int factor flag reg
		ld.b	[%r1],%r3			// clear Int factor flag

		// *** input data : unsigned 16-bit	stereo ***
		// *** output data : unsigned 15-bit  stereo ***

		ld.uh	%r4,[%r2]+			// read data
		add 	%r4,0x1 			// Change 16bit to 15bit
		srl 	%r4,0x1 			// Data >>=1 
		ld.w	%r3,%r4
		srl 	%r3,6				// %r3 is upper 9-bit,
		xand	%r4,0x3f
		xld.w	%r1,COMPARE_A16_1	// PWM data write reg
		ld.h	[%r1],%r3			// upper 9-bit
		add 	%r1,COMPARE_A16_2	// 
		ld.h	[%r1],%r4			// lower 6-bit 

		ld.uh	%r4,[%r2]+			// read data
		add 	%r4,0x1 			// Change 16bit to 15bit
		srl 	%r4,0x1 			// Data >>=1 
		ld.w	%r3,%r4
		srl 	%r3,6				// %r3 is upper 9-bit,
		xand	%r4,0x3f			// %r4 is lower 6-bit
		add 	%r1,COMPARE_A16_3	// PWM data write reg
		ld.h	[%r1],%r3			// upper 9-bit
		add 	%r1,COMPARE_A16_4	// 
		ld.h	[%r1],%r4			// lower 6-bit 



		ext 	OFFSET_TAIL 		// read TAIL
		ld.w	%r3,[%r0]
		cmp 	%r2,%r3 			// if (HEAD >= TAIL) Next
		jruge	PacketEnd
		ld.w	[%r0],%r2			// update HEAD
		popn	%r4
		reti

PacketEnd:								  // Next
		popn	%r4
		pushn	%r15
		ld.w	%r0,%ahr
		ld.w	%r1,%alr
		pushn	%r1
		xld.w	%r6,SPK_PARAMS_0			// SpkParams
		xld.w	%r7,TIMER16_5_IFLAG		// IFlagReg
		xld.w	%r8,TIMER16_ODD_UNDERFLOW	// IFlag MaskData
		ld.w	%r9,[%sp+0x12] 			// OldPSR
		xcall	QueueNext
		popn	%r1
		ld.w	%alr,%r1
		ld.w	%ahr,%r0
		popn	%r15
		reti