mem_init.c

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

//=========================================================================
//
//     This confidential and proprietary source code may be used only as
//     authorized by a licensing agreement from SEIKO EPSON CORPORATION.
//
//                (C) COPYRIGHT 2003 SEIKO EPSON CORPORATION.
//            (C) COPYRIGHT 2003 SHANGHAI EPSON ELECTRONIC CO.,LTD.
//                          ALL RIGHTS RESERVED
//
//     The entire notice above must be reproduced on all authorized copies
//     and any such reproduction must be pursuant to a licensing agreement
//     from SEIKO EPSON CORPORATION.
//
//	memory map		CEF must be 1x
//				internal RAM (16K)	0000-4000
//				internal VRAM(40K)	3c0000-3c9FFF   (48M OSC3 24 M bus 1wait)
//				internal 512K		2000000-2007FFF (512KB 16-bit SRAM area 13)
//				flash			c00000-cfffff	(1MB 16-bit Flash)
//=========================================================================

#include "bcu.h"
#include "osc.h"



/****************************************************************************
 * _init_bcu
 *   Type:     void
 *   Ret val:  none
 *   Argument: void
 *   Function: BCU initialization program.
 ****************************************************************************/
void _init_bcu(void)
{

  //set CEF=1x
  *(volatile unsigned short*)0x48130 =0x0c00;
  //Set all areas bus speed by #X2SPD
  *(volatile unsigned char*)0x4813e =0x00;
  //Set all areas read hold not inserted
  *(volatile unsigned char*)0x4813c =0x00;
  //Set BSL system & SWAIT enable
  *(volatile unsigned char*)0x4812e|=0x09;      //BSL system
//  *(volatile unsigned char*)0x4812e|=0x01;      //A0 system



  // Area 6 are internal extend peripheral IO, & 40k internal vram (16-bits)
  // 0-wait, 0.5-output-disable
  *(volatile unsigned short *)0x4812a = BCU_SZH_16 | BCU_DFH_05 | BCU_WTH_0;

  // Area 9 & 10 is external SRAM/ROM (16-bits)
  // 2-wait, 0.5-output-disable
  *(volatile unsigned short *)0x48126 = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_2;
  
  // Area 11 (internal external IO) 8bit
  // 2-wait,0.5-output-disable
  *(volatile unsigned short *)0x48124 = BCU_SZL_8 | BCU_DFL_05 | BCU_WTL_2;

  // Area 13 & 14 is external SDRAM (16-bits)
  // 0-wait, 0.5-output-disable
  *(volatile unsigned short *)0x48122 = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_0;

  // Area 15 & 16 is external NAND Flash (16-bits)
  // 2-wait, 0.5-output-disable
  *(volatile unsigned short *)0x48120 = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_2;


  // Area 4 (USB DMA) & Area 6 & Area11(USB CTL) is the internal area
  *(volatile unsigned short *)0x48132 = BCU_A6IO_INT | BCU_A5IO_INT | BCU_A12IO_INT;



  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set X1/X2 speed mode
  *(volatile unsigned char *)0x300f39 = 0x00;


  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set A0/BSL mode
  *(volatile unsigned char *)0x300f38 = 0x01;       //BSL system
//  *(volatile unsigned char *)0x300f38 = 0x00;       //A0 system

}

void _init_sysclk(unsigned char sysclkdt)
{
  int i;
  // Set power control register protect flag write enable
  *(volatile unsigned char *)0x4019e = 0x96;
  // Change CPU clock to OSC1 clock
  *(volatile unsigned char *)0x40180 = OSC_CLKDT_11 | OSC_PSCON_OFF | OSC_CLKCHG_OSC1 |
                                             OSC_SOSC3_ON | OSC_SOSC1_ON;

  // Set power control register protect flag write enable
  *(volatile unsigned char *)0x4019e = 0x96;
  // Stop OSC3 clock
  *(volatile unsigned char *)0x40180 = OSC_CLKDT_11  | OSC_PSCON_OFF | OSC_CLKCHG_OSC1 |
                                             OSC_SOSC3_OFF | OSC_SOSC1_ON;


//48MHz

  // Set MISC control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set OSC3 divider
  *(volatile unsigned char *)0x300f30 = sysclkdt / 16;
  // Set MISC control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set PLL multipler
  *(volatile unsigned char *)0x300f31 = sysclkdt;



  // Set power control register protect flag write enable
  *(volatile unsigned char *)0x4019e = 0x96;
  // Run OSC3 clock
  *(volatile unsigned char *)0x40180 = OSC_CLKDT_11  | OSC_PSCON_OFF | OSC_CLKCHG_OSC1 |
                                             OSC_SOSC3_ON  | OSC_SOSC1_ON;

  // Delay 100ms
  for (i=0;i<133;i++);

  // Set power control register protect flag write enable
  *(volatile unsigned char *)0x4019e = 0x96;
  // Switch to OSC3 clock
  *(volatile unsigned char *)0x40180 = OSC_CLKDT_11  | OSC_PSCON_ON | OSC_CLKCHG_OSC3 |
                                             OSC_SOSC3_ON  | OSC_SOSC1_ON;

}

void _init_subclk(unsigned char subclkdt)
{

  int i;

  // Stop LCDC if it is operating
  if (*(volatile unsigned short *)0x380014 & 0x0002)
  {
        *(volatile unsigned short *)0x380014 = 0x0000;
        // Delay
        for (i=0;i<100000;i++);
  }

  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Disable SUBCLK
  *(volatile unsigned char *)0x300f37  = 0x1;

  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set clock source select from PLL/OSC3
  *(volatile unsigned char *)0x300f32  = subclkdt / 16;

  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set clock divide rate by /1, /2, or /4
  *(volatile unsigned char *)0x300f33  = subclkdt;

  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Enable SUBCLK
  *(volatile unsigned char *)0x300f37  = 0x00;

  // Set misc control register protect flag write enable
  *(volatile unsigned char *)0x300f2f = 0x96;
  // Set BCLG enable
  *(volatile unsigned char *)0x300f33 |= 0x80;
}

void _init_sdramc()
{

  int i;

  // Fix BCLK clock
  *(volatile unsigned char *)0x4812f|= 0x80;

  // Set SDRAM pin share
  // PA, P2, P6, and P5
  *(volatile unsigned char *)0x300f60 = 0x1a;       //PA2, #SDRAS, #SDCAS
  *(volatile unsigned char *)0x402dc|= 0x01;        //P30 wait function

  *(volatile unsigned char *)0x300044 = 0x05;       //#SDWE, SDCKE
  *(volatile unsigned char *)0x30004c = 0x57;       //DQM, SDA10, SDCLK
  *(volatile unsigned char *)0x30004a&= 0x3f;       //#SDCE
  *(volatile unsigned char *)0x30004a|= 0x80;       //#SDCE


  // Delay
  for (i=0;i<1000;i++);


  *(volatile unsigned short *)0x3a0204 = 0x0177;    //Auto Refresh count
  *(volatile unsigned short *)0x3a0206 = 0x008f;    //Disable Self Refresh
  *(volatile unsigned short *)0x3a0208 = 0x0002;    //SDRAM speed setup
  *(volatile unsigned short *)0x3a0200 = 0x000b;    //SDRAM size setup

    // SDRAM initial
  while (*(volatile unsigned short *)0x3a0202 != 0x0008)
    {
    *(volatile unsigned short *)0x3a0202 = 0x0002;                  //Pre-Charge

    for (i=0;i<2;i++);

    for (i=0;i<8;i++) *(volatile unsigned short *)0x3a0202 = 0x0001;//Auto-Refresh

    for (i=0;i<2;i++);

    *(volatile unsigned short *)0x3a0202 = 0x0004;                  //Mode-Register-Set

    for (i=0;i<2;i++);

  }


  *(volatile unsigned short *)0x3a0210 = 0x000f;    //Areas, High performance, IQB on

}

void _init_busarb(unsigned char arbwait)
{
  // X2 area no need read-hold; X1 area need read-hold
  *(volatile unsigned char*)0x4813c|= *(volatile unsigned short *)0x4813e;
  // SDRAM area no need read-hold always
  if (*(volatile unsigned short*)0x48130==0x0800)
        *(volatile unsigned char*)0x4813c&= 0xfb;    //Area 7 & 8
  else
        *(volatile unsigned char*)0x4813c&= 0xdf;    //Area 13 & 14


  // SDRAM low performance if X2 mode
  if (*(volatile unsigned char *)0x300f39==0x00)
        *(volatile unsigned short *)0x3a0210&= 0x07;


  // Enable BUSARB
  *(volatile unsigned short *)0x390000 = 0x0001;

  // Wait count of BUSARB
  *(volatile unsigned short *)0x390002 = arbwait;    //15-wait-cycle
}