u_device.c

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

			}
		}
	}
}

/*****************************************************************************	
 *
 *			: CSW
 *				: CSW
 *			: 
 *			: 
 *		:device_state			Device
 *				 device_flag			Device
 *				 tran_protocol			
 *				 tran_flag				
 *				 bulk_actual_tran_cnt	Bulk
 *				 bulk_tran_start_addr	Bulk
 *				 bulk_out_state			BulkOUT
 *
 *****************************************************************************/
void WaitCSWCmp(void)
{
	if( tran_flag.XferCmp ){
		/*  */

		tran_flag.XferCmp = 0;						/*  */

		device_state = DEV_WAIT_RCV_CMD;		/*  */

		ControlLED(PORT_TURN_OFF);				/* PORTLED */
	}
}

/*****************************************************************************
 *
 *			: CBW
 *				: CBW
 *			: 
 *			: 
 *		: bulk_in_state			Bulk IN
 *				  bulk_out_state		Bulk OUT
 *				  protocol_phase		
 *				  bulk_req_tran_cnt		Bulk
 *				  tran_flag				
 *				  cmd_block[]			
 *				  device_flag			Device
 *
 *****************************************************************************/
void CBWCheck(void)
{
	int i, j;
	
	if(cbw[0] != 0x55 || cbw[1] != 0x53 || cbw[2] != 0x42 || cbw[3] != 0x43){
		/* (dCBWSignature0x43425355) */

		rEPnControl_BP.EPrForceSTALL = 1;
		bulk_in_state  = BULK_IN_STALL;
		bulk_out_state = BULK_OUT_STALL;
		protocol_phase = RESET_WAIT;
	}else{
		/*  */

		/* Bulk */
		bulk_req_tran_cnt = MKDWORD(cbw[11], cbw[10], cbw[9], cbw[8]);

		/* CBWbCBWFlags */
		if(cbw[12] & 0x80){
			/* IN */
			tran_flag.Direction = DIR_IN;
		}else{
			/* OUT */
			tran_flag.Direction = DIR_OUT;
		}

		if(cbw[13]){
			/* bCBWLUNLUN */
			rEPnControl_BP.EPrForceSTALL = 1;
			bulk_in_state  = BULK_IN_STALL;
			bulk_out_state = BULK_OUT_STALL;
			protocol_phase = RESET_WAIT;
		} else {
			/* bCBWLengthCBWCDB */

			for( i=0, j=15; i<cbw[14]; i++, j++ ){
				cmd_block[i] = cbw[j];
			}

			/*  */
			device_flag.RcvCommand = 1;

		}
	}
}

/*****************************************************************************
 *
 *			: CSW
 *				: CSW
 *			: 
 *			: 
 *		: protocol_phase		
 *				  bulk_in_state			Bulk IN
 *				  bulk_out_state		Bulk OUT
 *				  cmd_status			
 *				  control_state			Control
 *				  bulk_req_tran_cnt		Bulk
 *				  bulk_total_tran_cnt	Bulk
 *
 *****************************************************************************/
void CSWSet(void)
{
	DWORD residue_cnt;


	/* bCSWTagbCBWTag */
	csw[4] = cbw[4];
	csw[5] = cbw[5];
	csw[6] = cbw[6];
	csw[7] = cbw[7];

	if(cmd_status != PHASE_ERROR){
		/* dCSWDataResidue */

		residue_cnt = bulk_req_tran_cnt - bulk_total_tran_cnt;
		csw[8]	= DWORD2BYTE_LL(residue_cnt);
		csw[9]	= DWORD2BYTE_LH(residue_cnt);
		csw[10] = DWORD2BYTE_HL(residue_cnt);
		csw[11] = DWORD2BYTE_HH(residue_cnt);
	}else{
		/* 
		 * dCSWDataResidue 0  
		 */
		csw[8]	= 0x00;
		csw[9]	= 0x00;
		csw[10] = 0x00;
		csw[11] = 0x00;

	}

	csw[12] = cmd_status;	/* bCSWStatus */

	
	tran_flag.DMA = 0;					/* DMA */
	bulk_actual_tran_cnt = 13;			/* Bulk */
	bulk_total_tran_cnt = bulk_req_tran_cnt;
	bulk_tran_start_addr = csw;			/*  */

	bulk_in_state = BULK_IN_DATA_SET;	/* BulkIN */

}

/*****************************************************************************
 *
 *     Device
 *     
 *   
 * tran_flag			 
 *			 device_flag		 
 *			 bulk_req_tran_cnt	  
 *			 bulk_total_tran_cnt  
 *			 bulk_actual_tran_cnt 
 *			 cmd_block			 ATAPI
 *			 sense_data 		 Sense KeyASCASCQ
 *			 atten_flag 		 
 *****************************************************************************/
void InitDeviceWorkArea(void)
{
	int i;
	
	/*  */
	tran_flag.XferCmp	= 0;
	tran_flag.Direction = DIR_OUT;
	tran_flag.DMA		= 0;
	
	device_flag.RcvCommand	= 0;
	device_flag.WaitCBW 	= 0;
	
	/*  */
	block_size = 512;
	
//	last_lba = RAMDSK_TOTAL_SEC;		// for Tateishi RAM-DISK 
										// u_idle.c setup after ATTACH

	ata_lba 			= 0;
	mode_data_cnt		= 0;
	bulk_tran_start_addr = 0;
	mode_data_addr		= 0;
	mode_chg_addr		= 0;
	bulk_req_tran_cnt	 = 0;
	bulk_total_tran_cnt  = 0;
	bulk_actual_tran_cnt = 0;
	test_unit_ready_cnt = 0;
	
	for (i = 0;i < 12;i++) {
		cmd_block[i] = 0;				/* ATAPI */
	}
	
	/* wk_data  */
	for (i = 0;i < sizeof(wk_data);i++) {
		wk_data[i] = 0x00;
	}
	
	/* bCSWSignature */
	csw[0] = 0x55;
	csw[1] = 0x53;
	csw[2] = 0x42;
	csw[3] = 0x53;
	
	/* Sense Key */
	sense_data[0] = 0x00;
	sense_data[1] = 0x00;
	sense_data[2] = 0x00;
	

	atten_flag.PowerOnReset = 1;	/*  */

}


/*****************************************************************************
 *
 *			: MasterDMA
 *				: DMA
 *			: 
 *			: 
 *		: protocol_phase		
 *				  bulk_in_state			Bulk IN
 *				  bulk_out_state		Bulk OUT
 *				  cmd_status			
 *				  control_state			Control
 *				  bulk_req_tran_cnt		Bulk
 *				  bulk_total_tran_cnt	Bulk
 *
 *****************************************************************************/
void MasterDMAStart(void)
{

	BYTE temp;

// 1.start HsDMA setting
	bHS3_EN_HS3EN  = 0;								/* HSDMA3 */

//		sram_start_addr = SRAM_START_ADDR ;	// u_idle.c setup after ATTACH
		

// 2.trigger & transfer mode setting
	bHSDMA_HTGR2_HSD3S = HS3_K54F;					/* K54(PDREQ */
	bHS3_TF_HS3TF = 1;								/*  */
	bHS3_CNT_BLK_DUALM3 = 1;						/*  */
	bHS3_DADR_D3MOD = 0x00;							/*  */

// 3.transfer Direction & transfer data size setting
	if( tran_flag.Direction == DIR_IN ){

		/* IN */					/*  */
//		bHS3_SADR_S3ADR = sram_start_addr + ((ata_lba*block_size) );	/* ext-RAM */
		bHS3_SADR_S3ADR = sram_start_addr ;								/* for DTQ method */
		bHS3_DADR_D3ADR = 0x100000 ;									/* Area 4 Nikka DMA area */
//		bHS3_DADR_D3ADR = 0x100001 ;									/* Area 4 Nikka DMA area */
		bHS3_SADR_S3IN = 0x03;											/* address inc(no init) */
		bHS3_DADR_D3IN = 0x00;											/* address fix */

	}else{

		/* OUT */					/*  */
		bHS3_SADR_S3ADR = 0x100000 ;									/* Area 4 Nikka DMA area */
//		bHS3_SADR_S3ADR = 0x100001 ;									/* Area 4 Nikka DMA area */
//		bHS3_DADR_D3ADR = sram_start_addr + ((ata_lba*block_size) );	/* ext-RAM */
		bHS3_DADR_D3ADR = sram_start_addr ;								/* for DTQ method */
		bHS3_SADR_S3IN = 0x00;											/* address fix */
		bHS3_DADR_D3IN = 0x03;											/* address inc(no init) */

	}

	bHS3_SADR_DATSIZE3 = 0;							/* byte size */
	bHS3_CNT_SIG_TC3 = bulk_actual_tran_cnt;		/* Bulk(8bit) */



	bINT_PHSD23L_PHSD3L = 7;						/* HDMA Ch.3 = 7 */
	
	bINT_FDMA_FHDM3 = 1;							/* HDMA Ch.3  */
	bINT_EDMA_EHDM3 = 0;							/* HDMA Ch.3  */
	bHS3_EN_HS3EN  = 1;								/* HSDMA3 */


}
/*****************************************************************************
 *
 *			: MasterDMA
 *				: DMA
 *			: 
 *			: 
 *		: protocol_phase		
 *				  bulk_in_state			Bulk IN
 *				  bulk_out_state		Bulk OUT
 *				  cmd_status			
 *				  control_state			Control
 *				  bulk_req_tran_cnt		Bulk
 *				  bulk_total_tran_cnt	Bulk
 *
 *****************************************************************************/
void MasterDMAStop(void)
{
	bHS3_EN_HS3EN  = 0;							/* DMAS */
}

//-----------------------------------------------------------------------------
// 
// 			 MasterDMA
// 
// 			 WRITE10
// 					
// 					
// 					WRITE10
// 
//-----------------------------------------------------------------------------

void MasterDMAXferEndProc(void)
{
	int retVal ;
	
//  1. pre-proces
	// High-speed DMA Ch.3 interrupt enable register
	//		#define bINT_EDMA_EHDM3 fINT_EDMA.EHDM3  
	bINT_EDMA_EHDM3 = 0 ;			// disable

	// High-speed DMA Ch.3 interrupt request flag register
	//		#define bINT_FDMA_FHDM3 fINT_FDMA.FHDM3  
	bINT_FDMA_FHDM3 = 1 ;			// clear

//  2. WRITE10 End process.
//	retVal = DrvFS_WriteSec(DRV_RAM, pc_rslt.ata_lba, pc_rslt.sec_cnt, &usb_wk_buf[0]);
	retVal = DrvFS_WriteSec(g_StgMediaInfo.type, g_UsbIFAns.ata_lba, g_UsbIFAns.sec_cnt, &usb_wk_buf[0]);

//  3. Command Error check
	if( retVal != 0 ){
		panic(42);	// nothing
	}
	
}