u_c33cpu.h

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

            unsigned short  Dummy   : 1;    /* DB reserve */
            unsigned short  A12IO   : 1;    /* Area 12.11 external/internal access */
            unsigned short  A14IO   : 1;    /* Area 14,13 external/internal access */
            unsigned short  A16IO   : 1;    /* Area 16,15 external/internal access */
            unsigned short  A18IO   : 1;    /* Area 18,17 external/internal access */
        } bCTL;
        volatile unsigned short usCTL;
    } rACCESS;

    volatile unsigned int   rTTBR;          /* Trap table base address register */

    union {                     /* [G/A read signal control register] rGA */
        volatile struct {
            unsigned short  A5RD    : 1;    /* Area 5,4 read signal */
            unsigned short  A6RD    : 1;    /* Area 6 read signal */
            unsigned short  A8RD    : 1;    /* Area 8,7 read signal */
            unsigned short  Dummy0  : 1;    /* D3 reserve */
            unsigned short  A12RD   : 1;    /* Area 12,11 read signal */
            unsigned short  A14RD   : 1;    /* Area 14,13 read signal */
            unsigned short  A16RD   : 1;    /* Area 16,15 read signal */
            unsigned short  A18RD   : 1;    /* Area 18,17 read signal */
            unsigned short  A5AS    : 1;    /* Area 5,4 address strobe signal */
            unsigned short  A6AS    : 1;    /* Area 6 address strobe signal */
            unsigned short  A8AS    : 1;    /* Area 8,7 address strobe signal */
            unsigned short  Dummy1  : 1;    /* DB reserve */
            unsigned short  A12AS   : 1;    /* Area 12,11 address strobe signal */
            unsigned short  A14AS   : 1;    /* Area 14,13 address strobe signal */
            unsigned short  A16AS   : 1;    /* Area 16,15 address strobe signal */
            unsigned short  A18AS   : 1;    /* Area 18,17 address strobe signal */
        } bCTL;
        volatile unsigned short usCTL;
    } rGA;

    volatile unsigned char  rBCLKSEL;       /* BCLK select register */

    unsigned char   Dummy1;
};

/****************************************************************/
/* [16-bit timer] c_T16                     */
/****************************************************************/
struct c_T16tag {
    volatile unsigned short rCRA;           /* 16-bit timer comparison data A set-up register */
    volatile unsigned short rCRB;           /* 16-bit timer comparison data B set-up register */
    volatile unsigned short rTC;            /* 16-bit timer counter data register */

    union {                     /* 16-bit timer control register */
        volatile struct {
            unsigned char   PRUN    : 1;    /* 16-bit timer Run/Stop control */
            unsigned char   PRESET  : 1;    /* 16-bit timer Reset */
            unsigned char   PTM : 1;    /* 16-bit timer clock output control */
            unsigned char   CKSL    : 1;    /* 16-bit timer input clock selection */
            unsigned char   OUTINV  : 1;    /* 16-bit timer output inversion */
            unsigned char   SELCRB  : 1;    /* 16-bit timer comparison buffer */
            unsigned char   SELFM   : 1;    /* 16-bit timer fine mode selection */
        } bCTL;
        volatile unsigned char  ucCTL;
    } rT16CTL;
    unsigned char   Dummy;
};

/****************************************************************/
/* [IDMA control register] c_IDMA               */
/****************************************************************/
struct c_IDMAtag {
    volatile unsigned int   rDBASE;         /* IDMA base address */

    union {                     /* IDMA start register */
        volatile struct {
            unsigned char   DCHN    : 7;    /* IDMA channel number */
            unsigned char   DSTART  : 1;    /* IDMA start */
        } bCTL;
        volatile unsigned char  ucCTL;
    } rSTART;

    union {                     /* IDMA enable register */
        volatile struct {
            unsigned char   IDMAEN  : 1;    /* IDMA enable */
        } bCTL;
        volatile unsigned char  ucCTL;
    } rIDMAEN;

    unsigned char   Dummy[2];
};

/****************************************************************/
/* [High-speed DMA control register] c_HSDMA            */
/****************************************************************/
struct c_HSDMAtag {
    union {                     /* High-speed DMA transfer counter/control register */
        /* Block transfer mode */
        volatile struct {
            unsigned int    BLKLEN  : 8;    /* Block length */
            unsigned int    TC  : 16;   /* Transfer counter[15:0] */
            unsigned int    Dummy   : 6;    /* DD-8 reserve */
            unsigned int    DIR : 1;    /* Transfer direction control (dual address mode) */
            unsigned int    DUALM   : 1;    /* Address mode selection */
        } bBLOCK;

        /* Single/successive transfer mode */
        volatile struct {
            unsigned int    TC  : 24;   /* Transfer counter[23:0] */
            unsigned int    Dummy   : 6;    /* DD-8 reserve */
            unsigned int    DIR : 1;    /* Transfer direction control (single address mode) */
            unsigned int    DUALM   : 1;    /* Address mode selection */
        } bSINGLE;

        volatile unsigned int   uiCTL;
    } rCNT;

    union {                     /* High-speed DMA source address set-up register */
        volatile struct {           /* (D):dual address mode, (S):single address mode */
            unsigned int    SADR    : 28;   /* Source address control(D)/memory address control(S) [27:0] */
            unsigned int    SIN : 2;    /* Source address control(D)/memory address control(S) */
            unsigned int    DATSIZE : 1;    /* Transfer data size */
            unsigned int    DINTEN  : 1;    /* Interrupt enable */
        } bCTL;
        volatile unsigned int   uiCTL;
    } rSADR;

    union {                     /* High-speed DMA destination set-up register */
        volatile struct {
            unsigned int    DADR    : 28;   /* Destination address(D) address control [27:0] */
            unsigned int    DIN : 2;    /* Destination address(D) address control */
            unsigned int    DMOD    : 2;    /* Transfer mode */
        } bCTL;
        volatile unsigned int   uiCTL;
    } rDADR;

    union {                     /* High-speed DMA enable register */
        volatile struct {
            unsigned short  HS_EN   : 1;    /* High-speed DMA enable */
        } bCTL;
        volatile unsigned short usCTL;
    } rHS_EN;

    union {                     /* High-speed DMA trigger flag register */
        volatile struct {
            unsigned short  HS_TF   : 1;    /* Trigger flag clear(WR)/trigger flag status(RD) */
        } bCTL;
        volatile unsigned short usCTL;
    } rTF;
};


/****************************************************************/
/* Address map I/O                      */
/****************************************************************/
struct c_IOtag {
    /*** 40000H *********************************************/
    unsigned char       Dummy0[326];        /* 0x40145 - 0x40000 */

    union c_CLKSELtag   c_CLKSEL_T8;        /* 8-bit timer clock selection register */

    union c_CLKCTLtag   c_CLKCTL_T16_0;     /* 16-bit timer0 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T16_1;     /* 16-bit timer1 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T16_2;     /* 16-bit timer2 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T16_3;     /* 16-bit timer3 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T16_4;     /* 16-bit timer4 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T16_5;     /* 16-bit timer5 clock control register */

    union c_CLKCTLtag   c_CLKCTL_T8_01;     /* 8-bit timer0/1 clock control register */
    union c_CLKCTLtag   c_CLKCTL_T8_23;     /* 8-bit timer2/3 clock control register */

    union c_CLKCTLtag   c_CLKCTL_AD;        /* A/D converter clock control register */

    unsigned char       Dummy1[1];      /* 0x40150 */

    struct c_TIMERtag   c_TIMER;        /* Clock timer */

    unsigned char       Dummy2[4];      /* 0x4015f - 0x4015c */

    struct c_T8tag      c_T8_0;         /* 8-bit timer 0 */
    struct c_T8tag      c_T8_1;         /* 8-bit timer 1 */
    struct c_T8tag      c_T8_2;         /* 8-bit timer 2 */
    struct c_T8tag      c_T8_3;         /* 8-bit timer 3 */

    struct c_WDTtag     c_WDT;          /* Watchdog timer */

    unsigned char       Dummy3[14];     /* 0x4017f - 0x40172 */

    struct c_PWRCTLtag  c_PWRCTL;       /* Power control */

    unsigned char       Dummy4[65];     /* 0x401df - 0x4019f */

    struct c_SIFtag     c_SIF0;         /* Serial I/F Ch.0 */
    struct c_SIFtag     c_SIF1;         /* Serial I/F Ch.1 */

    unsigned char       Dummy5[86];     /* 0x4023f - 0x401ea */

    struct c_ADtag      c_AD;           /* A/D converter */

    unsigned char       Dummy6[26];     /* 0x4025f - 0x40246 */

    struct c_INTCtag    c_INTC;         /* Interrupt controller */

    unsigned char       Dummy7[32];     /* 0x402bf - 0x402a0 */

    struct c_KPORTtag   c_KPORT;        /* Input port (K port) */

    unsigned char       Dummy8[1];      /* 0x402c5 */

    struct c_PINTtag    c_PINT;         /* Port input interrupt */

    struct c_PCTLtag    c_PCTL_P0;      /* Input/output port (P0 port) */
    struct c_PCTLtag    c_PCTL_P1;      /* Input/output port (P1 port) */
    struct c_PCTLtag    c_PCTL_P2;      /* Input/output port (P2 port) */
    struct c_PCTLtag    c_PCTL_P3;      /* Input/output port (P3 port) */

    unsigned char       Dummy9[32320];      /* 0x4811f - 0x402e0 */

    /*** 48000H *********************************************/

    struct c_BCUAREAtag c_BCUAREA;      /* BCU Area set-up */

    unsigned char       Dummy10[68];        /* 0x4817f - 0x4813c */

    struct c_T16tag     c_T16_0;        /* 16-bit timer 0 */
    struct c_T16tag     c_T16_1;        /* 16-bit timer 1 */
    struct c_T16tag     c_T16_2;        /* 16-bit timer 2 */
    struct c_T16tag     c_T16_3;        /* 16-bit timer 3 */
    struct c_T16tag     c_T16_4;        /* 16-bit timer 4 */
    struct c_T16tag     c_T16_5;        /* 16-bit timer 5 */

    unsigned char       Dummy11[80];        /* 0x481ff - 0x481b0 */

    struct c_IDMAtag    c_IDMA;         /* IDMA control register */

    unsigned char       Dummy12[24];        /* 0x4821f - 0x48208 */ /* Dummy (2byte) in c_IDMA */

    struct c_HSDMAtag   c_HSDMA0;       /* High-speed DMA Ch.0 */
    struct c_HSDMAtag   c_HSDMA1;       /* High-speed DMA Ch.1 */
    struct c_HSDMAtag   c_HSDMA2;       /* High-speed DMA Ch.2 */
    struct c_HSDMAtag   c_HSDMA3;       /* High-speed DMA Ch.3 */
};


/****************************************************************/
/*  Intelligent DMA(IDMA) control structure         */
/****************************************************************/
typedef struct {
    union {
        volatile struct {
            unsigned int    TC  : 24;   /* Data transfer counter */
            unsigned int    LINKCHN : 7;    /* IDMA link field */
            unsigned int    LINKEN  : 1;    /* IDAM link enable */
        } bBLK;

        volatile struct {
            unsigned int    BLKLEN  : 8;    /* Block size */
            unsigned int    TC  : 16;   /* Data transfer counter */
            unsigned int    LINKCHN : 7;    /* IDMA link field */
            unsigned int    LINKEN  : 1;    /* IDMA link enable */
        } bSIN;

        volatile unsigned int   uiTC;
    } rTC;

    union {
        volatile struct {
            unsigned int    SRADR   : 28;   /* Source address */
            unsigned int    SRINC   : 2;    /* Source address control */
            unsigned int    DATSIZ  : 1;    /* Data size control */
            unsigned int    DINTEN  : 1;    /* Interrupt en