📄 u_c33cpu.h
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} rSPPT;
union { /* Port input interrupt edge/level select register */
volatile struct {
unsigned char SEPT0 : 1; /* FPT0 edge/level selection */
unsigned char SEPT1 : 1; /* FPT1 edge/level selection */
unsigned char SEPT2 : 1; /* FPT2 edge/level selection */
unsigned char SEPT3 : 1; /* FPT3 edge/level selection */
unsigned char SEPT4 : 1; /* FPT4 edge/level selection */
unsigned char SEPT5 : 1; /* FPT5 edge/level selection */
unsigned char SEPT6 : 1; /* FPT6 edge/level selection */
unsigned char SEPT7 : 1; /* FPT7 edge/level selection */
} bSEPT;
volatile unsigned char ucSEPT;
} rSEPT;
union { /* Key input interrupt select register */
volatile struct {
unsigned char SPPK0 : 2; /* FPK0 interrupt input port selection */
unsigned char SPPK1 : 2; /* FPK1 interrupt input port selection */
} bSPPK;
volatile unsigned char ucSPPK;
} rSPPK;
unsigned char Dummy;
union { /* Key input interrupt (FPK0) input comparison register */
volatile struct {
unsigned char SCPK00 : 1; /* FPK00 input comparison */
unsigned char SCPK01 : 1; /* FPK01 input comparison */
unsigned char SCPK02 : 1; /* FPK02 input comparison */
unsigned char SCPK03 : 1; /* FPK03 input comparison */
unsigned char SCPK04 : 1; /* FPK04 input comparison */
} bSCPK0;
volatile unsigned char ucSCPK0;
} rSCPK0;
union { /* Key input interrupt (FPK1) input comparison register */
volatile struct {
unsigned char SCPK10 : 1; /* FPK10 input comparison */
unsigned char SCPK11 : 1; /* FPK11 input comparison */
unsigned char SCPK12 : 1; /* FPK12 input comparison */
unsigned char SCPK13 : 1; /* FPK13 input comparison */
} bSCPK1;
volatile unsigned char ucSCPK1;
} rSCPK1;
union { /* Key input interrupt (FPK0) input mask register */
volatile struct {
unsigned char SMPK00 : 1; /* FPK00 input mask */
unsigned char SMPK01 : 1; /* FPK01 input mask */
unsigned char SMPK02 : 1; /* FPK02 input mask */
unsigned char SMPK03 : 1; /* FPK03 input mask */
unsigned char SMPK04 : 1; /* FPK04 input mask */
} bSMPK0;
volatile unsigned char ucSMPK0;
} rSMPK0;
union { /* Key input interrupt (FPK1) input mask register */
volatile struct {
unsigned char SMPK10 : 1; /* FPK10 input mask */
unsigned char SMPK11 : 1; /* FPK11 input mask */
unsigned char SMPK12 : 1; /* FPK12 input mask */
unsigned char SMPK13 : 1; /* FPK13 input mask */
} bSMPK1;
volatile unsigned char ucSMPK1;
} rSMPK1;
};
/****************************************************************/
/* [Input/output port (P port)] c_PCTL */
/****************************************************************/
struct c_PCTLtag {
union { /* Function select register */
volatile struct {
unsigned char CFP0 : 1; /* PX0 */
unsigned char CFP1 : 1; /* PX1 */
unsigned char CFP2 : 1; /* PX2 */
unsigned char CFP3 : 1; /* PX3 */
unsigned char CFP4 : 1; /* PX4 */
unsigned char CFP5 : 1; /* PX5 */
unsigned char CFP6 : 1; /* PX6 */
unsigned char CFP7 : 1; /* PX7 */
} bCFP;
volatile unsigned char ucCFP;
} rCFP;
union { /* Input/output port data register */
volatile struct {
unsigned char P0D : 1; /* Bit0 */
unsigned char P1D : 1; /* Bit1 */
unsigned char P2D : 1; /* Bit2 */
unsigned char P3D : 1; /* Bit3 */
unsigned char P4D : 1; /* Bit4 */
unsigned char P5D : 1; /* Bit5 */
unsigned char P6D : 1; /* Bit6 */
unsigned char P7D : 1; /* Bit7 */
} bPD;
volatile unsigned char ucPD;
} rPD;
union { /* I/O control register */
volatile struct {
unsigned char IOC0 : 1; /* PX0 1:output 0:input */
unsigned char IOC1 : 1; /* PX1 1:output 0:input */
unsigned char IOC2 : 1; /* PX2 1:output 0:input */
unsigned char IOC3 : 1; /* PX3 1:output 0:input */
unsigned char IOC4 : 1; /* PX4 1:output 0:input */
unsigned char IOC5 : 1; /* PX5 1:output 0:input */
unsigned char IOC6 : 1; /* PX6 1:output 0:input */
unsigned char IOC7 : 1; /* PX7 1:output 0:input */
} bIOC;
volatile unsigned char ucIOC;
} rIOC;
union { /* Port function extension register */
volatile struct {
unsigned char CFEX0 : 1; /* CFEX0 P12, P14 port extended function */
unsigned char CFEX1 : 1; /* CFEX1 P10, P11, P13 port extended function */
unsigned char CFEX2 : 1; /* CFEX2 P21 port extended function */
unsigned char CFEX3 : 1; /* CFEX3 P31 port extended function */
unsigned char CFEX4 : 1; /* CFEX4 P04 port extended function */
unsigned char CFEX5 : 1; /* CFEX5 P05 port extended function */
unsigned char CFEX6 : 1; /* CFEX6 P06 port extended function */
unsigned char CFEX7 : 1; /* CFEX7 P07 port extended function */
} bCFEX;
volatile unsigned char ucCFEX;
} rCFEX;
};
/****************************************************************/
/* [BCU Area selection] c_BCUAREA */
/****************************************************************/
struct c_BCUAREAtag {
union { /* [Areas 18-15 set-up register] rA18_15 */
volatile struct {
unsigned short A16WT : 3; /* Areas 16-15 wait control */
unsigned short Dummy0 : 1; /* D3 reserve */
unsigned short A16DF : 2; /* Areas 16-15 output disable delay time */
unsigned short A16SZ : 1; /* Areas 16-15 device size selection */
unsigned short Dummy1 : 1; /* D7 reserve */
unsigned short A18WT : 3; /* Areas 18-17 wait control */
unsigned short Dummy2 : 1; /* DB reserve */
unsigned short A18DF : 2; /* Areas 18-17 output disable delay time */
unsigned short A18SZ : 1; /* Areas 18-17 device size selection */
} bCTL;
volatile unsigned short usCTL;
} rA18_15;
union { /* [Areas 14-13 set-up register] rA14_13 */
volatile struct {
unsigned short A14WT : 3; /* Areas 14-13 wait control */
unsigned short Dummy : 1; /* D3 reserve */
unsigned short A14DF : 2; /* Areas 14-13 output disable delay time */
unsigned short A14SZ : 1; /* Areas 14-13 device size selection */
unsigned short A13DRA : 1; /* Area 13 DRAM selection */
unsigned short A14DRA : 1; /* Area 14 DRAM selection */
} bCTL;
volatile unsigned short usCTL;
} rA14_13;
union { /* [Areas 12-11 set-up register] rA12_11 */
volatile struct {
unsigned short A12WT : 3; /* Areas 12-11 wait control */
unsigned short Dummy : 1; /* D3 reserve */
unsigned short A12DF : 2; /* Areas 12-11 output disable delay time */
unsigned short A12SZ : 1; /* Areas 12-11 device size selection */
} bCTL;
volatile unsigned short usCTL;
} rA12_11;
union { /* [Areas 10-9 set-up register] rA10_9 */
volatile struct {
unsigned short A10WT : 3; /* Areas 10-9 wait control */
unsigned short Dummy0 : 1; /* D3 reserve */
unsigned short A10DF : 2; /* Areas 10-9 output disable delay time */
unsigned short A10SZ : 1; /* Areas 10-9 device size selection */
unsigned short A9DRA : 1; /* Area 9 burst ROM selection */
unsigned short A10DRA : 1; /* Area 10 burst ROM selection */
unsigned short A10BW : 2; /* Areas 10-9 burst ROM burst read cycle wait control */
unsigned short Dummy1 : 1; /* D7 reserve */
unsigned short A10IR : 3; /* Area 10 internal ROM capacity selection */
} bCTL;
volatile unsigned short usCTL;
} rA10_9;
union { /* [Areas 8-7 set-up register] rA8_7 */
volatile struct {
unsigned short A8WT : 3; /* Areas 8-7 wait control */
unsigned short Dummy : 1; /* D3 reserve */
unsigned short A8DF : 2; /* Areas 8-7 output disable delay time */
unsigned short A8SZ : 1; /* Areas 8-7 device size selection */
unsigned short A7DRA : 1; /* Area 7 DRAM selection */
unsigned short A8DRA : 1; /* Area 8 DRAM selection */
} bCTL;
volatile unsigned short usCTL;
} rA8_7;
union { /* [Areas 6-4 set-up register] rA6_4 */
volatile struct {
unsigned short A5WT : 3; /* Areas 5-4 wait control */
unsigned short Dummy0 : 1; /* D3 reserve */
unsigned short A5DF : 2; /* Areas 5-4 output disable delay time */
unsigned short A5SZ : 1; /* Areas 5-4 device size selection */
unsigned short Dummy1 : 1; /* D7 reserve */
unsigned short A6WT : 3; /* Area 6 wait control */
unsigned short Dummy2 : 1; /* DB reserve */
unsigned short A6DF : 2; /* Area 6 output disable delay time */
} bCTL;
volatile unsigned short usCTL;
} rA6_4;
unsigned char Dummy0;
volatile unsigned char rTBRP; /* TTBR write protection register */
union { /* [Bus control register] rBUS */
volatile struct {
unsigned short SWAITE : 1; /* #WAIT enable */
unsigned short SEPD : 1; /* External power-down control */
unsigned short SEMAS : 1; /* External bus master set-up */
unsigned short SBUSST : 1; /* External interface method selection */
unsigned short S2WE : 1; /* DRAM interface method selection */
unsigned short RRA : 2; /* Refresh RAS pulse width selection */
unsigned short RPC0 : 1; /* Refresh RPC delay set-up */
unsigned short RPC1 : 1; /* Refresh method selection */
unsigned short RPC2 : 1; /* Refresh enable */
unsigned short RCA : 2; /* Column address size selection */
unsigned short REDO : 1; /* DRAM page mode selection */
unsigned short RBST8 : 1; /* Burst ROM burst mode selection */
unsigned short Dummy : 1; /* DE reserve */
unsigned short RBCLK : 1; /* BCLK output control */
} bCTL;
volatile unsigned short usCTL;
} rBUS;
union { /* [DRAM timing set-up register] rDRAM */
volatile struct {
unsigned short RASC : 2; /* DRAM RAS cycle selection */
unsigned short Dummy0 : 1; /* Reserve */
unsigned short CASC : 2; /* DRAM CAS cycle selection */
unsigned short Dummy1 : 1; /* Reserve */
unsigned short RPRC : 2; /* DRAM RAS precharge cycle selection */
unsigned short CRAS : 1; /* Successive RAS mode */
unsigned short CEFUNC : 2; /* #CE pin function selection */
unsigned short A3EEN : 1; /* Area 3 emulation */
} bCTL;
volatile unsigned short usCTL;
} rDRAM;
union { /* [Access control register] rACCESS */
volatile struct {
unsigned short A5EC : 1; /* Area 5,4 endian control */
unsigned short A6EC : 1; /* Area 6 endian control */
unsigned short A8EC : 1; /* Area 8,7 endian control */
unsigned short A10EC : 1; /* Area 10,9 endian control */
unsigned short A12EC : 1; /* Area 12,11 endian control */
unsigned short A14EC : 1; /* Area 14,13 endian control */
unsigned short A16EC : 1; /* Area 16,15 endian control */
unsigned short A18EC : 1; /* Area 18,17 endian control */
unsigned short A5IO : 1; /* Area 5,4 external/internal access */
unsigned short A6IO : 1; /* Area 6 external/internal access */
unsigned short A8IO : 1; /* Area 8,7 external/internal access */
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