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📄 u_c33cpu.h

📁 The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F
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    union {                     /* Key input 0/1 interrupt priority register */
        volatile struct {
            unsigned char   PK0L    : 3;    /* Key input 0 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PK1L    : 3;    /* Key input 1 interrupt priority level */
        } bPK01L;
        volatile unsigned char  ucPK01L;
    } rPK01L;

    union {                     /* High-speed DMA Ch.0/1 interrupt priority register */
        volatile struct {
            unsigned char   PHSD0L  : 3;    /* High-speed DMA Ch.0 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PHSD1L  : 3;    /* High-speed DMA Ch.1 interrupt priority level */
        } bPHSD01L;
        volatile unsigned char  ucPHSD01L;
    } rPHSD01L;

    union {                     /* High-speed DMA Ch.2/3 interrupt priority register */
        volatile struct {
            unsigned char   PHSD2L  : 3;    /* High-speed DMA Ch.2 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PHSD3L  : 3;    /* High-speed DMA Ch.3 interrupt priority level */
        } bPHSD23L;
        volatile unsigned char  ucPHSD23L;
    } rPHSD23L;

    volatile unsigned char  rPDM;           /* IDMA interrupt priority register */

    union {                     /* 16-bit timer 0/1 interrupt priority register */
        volatile struct {
            unsigned char   P16T0   : 3;    /* 16-bit timer 0 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   P16T1   : 3;    /* 16-bit timer 1 interrupt priority level */
        } bP16T01;
        volatile unsigned char  ucP16T01;
    } rP16T01;

    union {                     /* 16-bit timer 2/3 interrupt priority register */
        volatile struct {
            unsigned char   P16T2   : 3;    /* 16-bit timer 2 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   P16T3   : 3;    /* 16-bit timer 3 interrupt priority level */
        } bP16T23;
        volatile unsigned char  ucP16T23;
    } rP16T23;

    union {                     /* 16-bit timer 4/5 interrupt priority register */
        volatile struct {
            unsigned char   P16T4   : 3;    /* 16-bit timer 4 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   P16T5   : 3;    /* 16-bit timer 5 interrupt priority level */
        } bP16T45;
        volatile unsigned char  ucP16T45;
    } rP16T45;

    union {                     /* 8-bit timer 0-3, serial I/F Ch.0 interrupt priority register */
        volatile struct {
            unsigned char   P8TM    : 3;    /* 8-bit timer 0-3 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PSIO0   : 3;    /* Serial I/F Ch.0 interrupt priority level */
        } bP8TM_PSIO0;
        volatile unsigned char  ucP8TM_PSIO0;
    } rP8TM_PSIO0;

    union {                     /* Serial I/F Ch.1 and A/D converter interrupt priority register */
        volatile struct {
            unsigned char   PSIO1   : 3;    /* Serial I/F Ch.1 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PAD : 3;    /* A/D converter interrupt priority level */
        } bPSIO1_PAD;
        volatile unsigned char  ucPSIO1_PAD;
    } rPSIO1_PAD;

    volatile unsigned char  rPCTM;          /* Clock timer interrupt priority register */

    union {                     /* Port input 4/5 interrupt priority register */
        volatile struct {
            unsigned char   PP4L    : 3;    /* Port input 4 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PP5L    : 3;    /* Port input 5 interrupt priority level */
        } bPP45L;
        volatile unsigned char  ucPP45L;
    } rPP45L;

    union {                     /* Port input 6/7 interrupt priority register */
        volatile struct {
            unsigned char   PP6L    : 3;    /* Port input 6 interrupt priority level */
            unsigned char   Dummy   : 1;
            unsigned char   PP7L    : 3;    /* Port input 7 interrupt priority level */
        } bPP67L;
        volatile unsigned char  ucPP67L;
    } rPP67L;

    unsigned char   Dummy0[2];

    union {                     /* Key input, port input 0-3 interrupt request flag register */
        volatile struct {
            unsigned char   EP0 : 1;    /* Port input 0 */
            unsigned char   EP1 : 1;    /* Port input 1 */
            unsigned char   EP2 : 1;    /* Port input 2 */
            unsigned char   EP3 : 1;    /* Port input 3 */
            unsigned char   EK0 : 1;    /* Key input 0 */
            unsigned char   EK1 : 1;    /* Key input 1 */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN1;

    union {                     /* DMA interrupt enable register */
        volatile struct {
            unsigned char   EHDM0   : 1;    /* High-speed DMA Ch.0 */
            unsigned char   EHDM1   : 1;    /* High-speed DMA Ch.1 */
            unsigned char   EHDM2   : 1;    /* High-speed DMA Ch.2 */
            unsigned char   EHDM3   : 1;    /* High-speed DMA Ch.3 */
            unsigned char   EIDMA   : 1;    /* IDMA */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN2;

    union {                     /* 16-bit timer 0/1 interrupt enable register */
        volatile struct {
            unsigned char   Dummy0  : 2;    /* D1-0 reserved */
            unsigned char   E16TU0  : 1;    /* 16-bit timer 0 comparison B */
            unsigned char   E16TC0  : 1;    /* 16-bit timer 0 comparison A */
            unsigned char   Dummy1  : 2;    /* D5-4 reserved */
            unsigned char   E16TU1  : 1;    /* 16-bit timer 1 comparison B */
            unsigned char   E16TC1  : 1;    /* 16-bit timer 1 comparison A */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN3;

    union {                     /* 16-bit timer 2/3 interrupt enable register */
        volatile struct {
            unsigned char   Dummy0  : 2;    /* D1-0 reserved */
            unsigned char   E16TU2  : 1;    /* 16-bit timer 2 comparison B */
            unsigned char   E16TC2  : 1;    /* 16-bit timer 2 comparison A */
            unsigned char   Dummy1  : 2;    /* D5-4 reserved */
            unsigned char   E16TU3  : 1;    /* 16-bit timer 3 comparison B */
            unsigned char   E16TC3  : 1;    /* 16-bit timer 3 comparison A */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN4;

    union {                     /* 16-bit timer 4/5 interrupt enable register */
        volatile struct {
            unsigned char   Dummy0  : 2;    /* D1-0 reserved */
            unsigned char   E16TU4  : 1;    /* 16-bit timer 4 comparison B */
            unsigned char   E16TC4  : 1;    /* 16-bit timer 4 comparison A */
            unsigned char   Dummy1  : 2;    /* D5-4 reserved */
            unsigned char   E16TU5  : 1;    /* 16-bit timer 5 comparison B */
            unsigned char   E16TC5  : 1;    /* 16-bit timer 5 comparison A */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN5;

    union {                     /* 8-bit timer interrupt enable register */
        volatile struct {
            unsigned char   E8TU0   : 1;    /* 8-bit timer 0 underflow */
            unsigned char   E8TU1   : 1;    /* 8-bit timer 1 underflow */
            unsigned char   E8TU2   : 1;    /* 8-bit timer 2 underflow */
            unsigned char   E8TU3   : 1;    /* 8-bit timer 3 underflow */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN6;

    union {                     /* Serial I/F interrupt enable register */
        volatile struct {
            unsigned char   ESERR0  : 1;    /* Serial I/F Ch.0 receive error */
            unsigned char   ESRX0   : 1;    /* Serial I/F Ch.0 receive buffer full */
            unsigned char   ESTX0   : 1;    /* Serial I/F Ch.0 transmit buffer empty */
            unsigned char   ESERR1  : 1;    /* Serial I/F Ch.1 receive error */
            unsigned char   ESRX1   : 1;    /* Serial I/F Ch.1 receive buffer full */
            unsigned char   ESTX1   : 1;    /* Serial I/F Ch.1 transmit buffer empty */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN7;

    union {                     /* Port input 4-7, clock timer, A/D interrupt enable register */
        volatile struct {
            unsigned char   EADE    : 1;    /* A/D converter */
            unsigned char   ECTM    : 1;    /* Clock timer */
            unsigned char   EP4 : 1;    /* Port input 4 */
            unsigned char   EP5 : 1;    /* Port input 5 */
            unsigned char   EP6 : 1;    /* Port input 6 */
            unsigned char   EP7 : 1;    /* Port input 7 */
        } bIEN;
        volatile unsigned char  ucIEN;
    } rIEN8;

    unsigned char   Dummy1[8];

    union {                     /* Key input, port input 0-3 interrupt request flag register */
        volatile struct {
            unsigned char   FP0 : 1;    /* Port input 0 */
            unsigned char   FP1 : 1;    /* Port input 1 */
            unsigned char   FP2 : 1;    /* Port input 2 */
            unsigned char   FP3 : 1;    /* Port input 3 */
            unsigned char   FK0 : 1;    /* Key input 0 */
            unsigned char   FK1 : 1;    /* Key input 1 */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR1;

    union {                     /* DMA interrupt request flag register */
        volatile struct {
            unsigned char   FHDM0   : 1;    /* High-speed DMA Ch.0 */
            unsigned char   FHDM1   : 1;    /* High-speed DMA Ch.1 */
            unsigned char   FHDM2   : 1;    /* High-speed DMA Ch.2 */
            unsigned char   FHDM3   : 1;    /* High-speed DMA Ch.3 */
            unsigned char   FIDMA   : 1;    /* IDMA */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR2;

    union {                     /* 16-bit timer 0/1 interrupt request flag register */
        volatile struct {
            unsigned char   Dummy0  : 2;    /* D1-0 reserved */
            unsigned char   F16TU0  : 1;    /* 16-bit timer 0 comparison B */
            unsigned char   F16TC0  : 1;    /* 16-bit timer 0 comparison A */
            unsigned char   Dummy1  : 2;    /* D5-4 reserved */
            unsigned char   F16TU1  : 1;    /* 16-bit timer 1 comparison B */
            unsigned char   F16TC1  : 1;    /* 16-bit timer 1 comparison A */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR3;

    union {                     /* 16-bit timer 2/3 interrupt request flag register */
        volatile struct {
            unsigned char   Dummy2  : 2;    /* D1-0 reserved */
            unsigned char   F16TU2  : 1;    /* 16-bit timer 2 comparison B */
            unsigned char   F16TC2  : 1;    /* 16-bit timer 2 comparison A */
            unsigned char   Dummy3  : 2;    /* D5-4 reserved */
            unsigned char   F16TU3  : 1;    /* 16-bit timer 3 comparison B */
            unsigned char   F16TC3  : 1;    /* 16-bit timer 3 comparison A */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR4;

    union {                     /* 16-bit timer 4/5 interrupt request flag register */
        volatile struct {
            unsigned char   Dummy4  : 2;    /* D1-0 reserved */
            unsigned char   F16TU4  : 1;    /* 16-bit timer 4 comparison B */
            unsigned char   F16TC4  : 1;    /* 16-bit timer 4 comparison A */
            unsigned char   Dummy5  : 2;    /* D5-4 reserved */
            unsigned char   F16TU5  : 1;    /* 16-bit timer 5 comparison B */
            unsigned char   F16TC5  : 1;    /* 16-bit timer 5 comparison A */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR5;

    union {                     /* 8-bit timer interrupt request flag register */
        volatile struct {
            unsigned char   F8TU0   : 1;    /* 8-bit timer 0 underflow */
            unsigned char   F8TU1   : 1;    /* 8-bit timer 1 underflow */
            unsigned char   F8TU2   : 1;    /* 8-bit timer 2 underflow */
            unsigned char   F8TU3   : 1;    /* 8-bit timer 3 underflow */
        } bISR;
        volatile unsigned char  ucISR;
    } rISR6;

    union {                     /* Serial I/F interrupt request flag register */
        volatile struct {
            unsigned char   FSERR0  : 1;    /* Serial I/F Ch.0 receive error */
            unsigned char   FSRX0   : 1;    /* Serial I/F Ch.0 receive buffer full */

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