drv_nf.h

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

//    template.h    v1.0    2003/08/28

//--------------------------------------------------------------------------------- 
//
//      Copyright (C) SEIKO EPSON CORP. 2004
//
//      GROUP            	: SEE LSI
//      FILE                    : drv_nf.c
//      MODULE                  : nand flash module 
//                                
//
//      Function description    : head file of nand flash
//      Revision history        :                                                                                               
//                                Date            userName         Description
//                                2004/02/20      Stella	       start
//
//      Notes                   :
//
//---------------------------------------------------------------------------------

#ifndef _DRV_NF_H
#define _DRV_NF_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------------
// Constants (#define)
//---------------------------------------------------------------------------------

//---------------------------------------------------------------------------------
//Conditional assemble definition
//---------------------------------------------------------------------------------
//#define DEBUG

//#define BOOT
//#define BOOT_16
//#define BOOT_L05

#define ECC

#ifdef BOOT
	#define MAX_LD_CNT  30

#else
	#define MAX_LD_CNT  64
#endif 


#define DOWNLOAD_FUN 	fnFlash_PageWrite
#define FLASH_INIT	fnFlash_Init
#define ERASE_FUN 	fnFlash_BlockErase

 
/*Flash command	*/								
#define	 READ_MODE1_CMD		0x0000
#define  READ_ADV_CMD     	0x0030
#define	 READ_MODE2_CMD		0x0001
#define	 READ_MODE3_CMD		0x0050
#define  AUTO_WRITE_CMD		0x0080
#define  PAGE_WRITE_CMD		0x0010
#define  READ_STATUS_CMD	0x0070
#define  AUTO_ERASE_CMD		0x0060
#define  ERASE_CMD		0x00D0
#define	 RESET_CMD		0x00ff
#define  READ_ID      		0x0090
#define  READ_ID_ADDR	 	0x0000

//flash device information const
#define	TOTAL_SIZE		0x1000000
#define MAX_BLK_NUM 		1024		// mcp
#define MAX_PG_NUM 		0x20  		//32
#define PG_SIZE  		0x200
#define BLK_SIZE 		0x4000

#define	NAND_Flash_BASE_ADDRESS	0x4000000 	//both flash and SMC map to area 15


#define	FLASH_SUCCESS		0x0 
#define	FLASH_FAILED		0x1 
#define	FLASH_PAR_ERR		0x2
#define	FLASH_DATA_ERR		0x4
#define	FLASH_TIME_OUT_ERR	0x5
#define	FLASH_WRITE_ERR		0x6
#define	FLASH_ERASE_ERR		0x7
#define	FLASH_ECC_ERROR		0x8
#define FLASH_ID_ERROR      	0x9
#define FLASH_BUF_FLUSH 	0xa		// Spooling data flushed
#define FLASH_BUF_CLEAR		0xb		// Buffer address clear


//---------------------------------------------------------------------------------
// macro definition
//---------------------------------------------------------------------------------
/* control port register */
#define	SET_ALE_OUTPUT		*(volatile unsigned char*)0x402da|=0x20		//p25	
#define SET_CLE_OUTPUT		*(volatile unsigned char*)0x402da|=0x10		//p24

#define	SET_ALE_H		*(volatile unsigned char*)0x402d9|=0x20		//set p25 H	
#define	SET_ALE_L		*(volatile unsigned char*)0x402d9&=0xdf		//set p25 L	

#define SET_CLE_H		*(volatile unsigned char*)0x402d9|=0x10		//set p24 H
#define SET_CLE_L		*(volatile unsigned char*)0x402d9&=0xef		//set p24 L

#define SET_WP_OUTPUT		*(volatile unsigned char*)0x300021|=0x01	// set P40 output
#define SET_WP_H		*(volatile unsigned char*)0x300020|=0x01    	// set P40 high
#define SET_WP_L		*(volatile unsigned char*)0x300020&=0xfe    	// set P40 low
#define SET_WP_GPIO		*(volatile unsigned char*)0x300048|=0x01    	// set P40 as GPIO, not A25

#define SET_BUSY_INPUT		*(volatile unsigned char*)0x300f47&=0xdf 	// set PD5 input
#define CHECK_BUSY		(*(volatile unsigned char*)0x300f46 & 0x20 )	// PD5=L mean busy

//Dual address DMA setting (ch2)
#define DMA_DUAL 	  	*(volatile unsigned short*)0x48242 = 0x8000 	//  dual address mode
#define DMA_EN  		*(volatile unsigned char*)0x4824c |= 0x01 	// enable Ch.2 DMA 
#define DMA_TRIG  		*(volatile unsigned char*)0x4029a |= 0x04 	// software trigger Ch.2 DMA 

#define CHECK_DMA_END		(*(volatile unsigned char*)0x4824c & 0x01 )

// ECC setting
#define EN_ECC			*(volatile unsigned char*)0x300102|=0x01 	// enable ecc check
#define DIS_ECC			*(volatile unsigned char*)0x300102 &=0xfe	// disable ecc check
#define SET_DEVICE_16		*(volatile unsigned char*)0x300103|=0x01 	// 16 bit device
#define SET_DEVICE_8		*(volatile unsigned char*)0x300103&=0xfe 	// 8 bit device
#define RESET_ECC		*(volatile unsigned char*)0x300101|=0x01 	// reset ECC 
#define CHECK_ECC_READY		(*(volatile unsigned char*)0x300101& 0x1) 	// if can start ecc check

#define ECC_AREA0_COL_ADDR	(unsigned char*)0x300104


/* nand flash only control port register */
#define SET_NAND_CE_OUTPUT	*(volatile unsigned char*)0x300023|=0x02	//set P51 output
#define SET_NAND_CE_H		*(volatile unsigned char*)0x300022|=0x2		//set CE H
#define SET_NAND_CE_L		*(volatile unsigned char*)0x300022&=0xfd	//set CE L
#define SET_NAND_CE_CE		*(volatile unsigned char*)0x30004a &=0xf3	// set p51 as CE15&16 for CE don't-care flash
#define SET_NAND_CE_GPIO	*(volatile unsigned char*)0x30004a |=0x4 	// set p51 as GPIO

/*smt only control port register*/
#define SET_SMC_CE_OUTPUT	*(volatile unsigned char*)0x300023|=0x10 	//set P54 output
#define SET_SMC_CE_H		*(volatile unsigned char*)0x300022|=0x10	//set CE H
#define SET_SMC_CE_L		*(volatile unsigned char*)0x300022&=0xef    	//set CE L
#define SET_SMC_CE_GPIO 	*(volatile unsigned char*)0x30004b |=0x01	// set p54 as GPIO

#define CLR_SMIFREG		*(volatile unsigned char*)0x300047&=0xf0	// clear smart media i/f lower 4 bit
#define SET_SMIF_WE		*(volatile unsigned char*)0x300047|=0x01	// set p34 as SMWE
#define SET_SMIF_RD		*(volatile unsigned char*)0x300047|=0x04	// set p35 as SMRD

#define SET_NAND_AREA		*(volatile unsigned char*)0x300100=0x0  	// not select boot mode , area 15; both SMC, flash all map to area 15




#ifdef __cplusplus
}
#endif

#endif //_DRV_NF_H