boot_loader_0.c

The combined demo is dedicated for S1C33L05, so DMT33L05 should be used to load and run the demo. F

//--------------------------------------------------------------------------------- 
//
//      Copyright (C) SEIKO EPSON CORP. 2004 
//
//      GROUP           : SEE LSI
//      FILE                    : boot_loader_0.c
//      MODULE                  : nand flash booting
//      Function description    : first boot code put in page0/block0 of boot nand flash
//      Revision history        :                                                                                               
//                                Date            userName         Description
//                                2004/02/24      Stella          start
//
//      Notes                   : 
//
//---------------------------------------------------------------------------------



#define SRAM_BOOT_ADDR      0x200           /* jump destination address*/
#define ECC                                 /* ECC check enable*/


/*Flash command */                              
#define  READ_MODE1_CMD     0x0000
#define  NAND_Flash_BASE_ADDRESS    0x4000000   /*both flash and SMC map to area 15*/

#define  FLASH_ECC_ERROR        0x1

//---------------------------------------------------------------------------------
// macro definition
//---------------------------------------------------------------------------------
#define SET_BUSY_INPUT      *(volatile unsigned char*)0x300f47&=0xdf    /* set PD5 input*/
#define CHECK_BUSY      (*(volatile unsigned char*)0x300f46 & 0x20 )    /* PD5=L mean busy*/
#define SET_ALE_H       *(volatile unsigned char*)0x402d9|=0x20     //set p25 H 
#define SET_ALE_L       *(volatile unsigned char*)0x402d9&=0xdf     //set p25 L 

#define SET_CLE_H       *(volatile unsigned char*)0x402d9|=0x10     //set p24 H
#define SET_CLE_L       *(volatile unsigned char*)0x402d9&=0xef     //set p24 L


/* ECC setting*/
#define EN_ECC          *(volatile unsigned char*)0x300102|=0x01    /* enable ecc check*/
#define DIS_ECC         *(volatile unsigned char*)0x300102 &=0xfe   /* disable ecc check*/
#define SET_DEVICE_16       *(volatile unsigned char*)0x300103|=0x01    /* 16 bit device*/
#define RESET_ECC       *(volatile unsigned char*)0x300101|=0x01    /* reset ECC */
#define CHECK_ECC_READY     (*(volatile unsigned char*)0x300101& 0x1)   /* if can start ecc check*/
#define ECC_AREA0_COL_ADDR  (unsigned char*)0x300104

/* nand flash only control port register */
#define SET_NAND_CE_CE      *(volatile unsigned char*)0x30004a &=0xf3   /* set p51 as CE15&16 for CE don't-care flash*/


typedef void (*pFunc)();
/*******************************************************************************
 * boot
 *   Type : void
 *   Ret val :  none
 *   Argument : void
 *   Function : Boot program. This is the 1st boot area, store in 1nd page of nand flash
 *******************************************************************************/
int SRAM_BOOT(void)
{
        unsigned short ReadCnt,i;
        unsigned short *ECCRet;
        unsigned short getRedt[3];
        
    unsigned long * test;
    
    
    pFunc       JP_ADDR;
 
    asm("xld.w  %r4,0x3fff");   /* Set SP in end of 16KB internal RAM*/
    asm("ld.w   %sp,%r4");
    
    test=(unsigned long*)500;
    *test=(unsigned long)SRAM_BOOT_ADDR;
    JP_ADDR=(pFunc)*test;
        
        
        /*CEFUNC seting 1x*/
    *(volatile unsigned char*)0x48131=0x04;


    /*select CE/GPIO port function as CE*/
    SET_NAND_CE_CE;
    /* set flash device mode*/
    SET_DEVICE_16;  
    /*set by/ry signal as input*/
    SET_BUSY_INPUT; 
    
 
    
    /*read page0/block1 data from nand flash sdram init and copy user code from nand flash to sdram*/
     SET_CLE_H;     /* set CLE H*/
     *(volatile unsigned short*)NAND_Flash_BASE_ADDRESS=READ_MODE1_CMD; /* read mode 1*/
     SET_CLE_L;     /* set CLE low*/
     SET_ALE_H;     /* set ALE h*/
    
        
     *(volatile unsigned short*)NAND_Flash_BASE_ADDRESS=0x0;    /* send col address*/
     *(volatile unsigned short*)NAND_Flash_BASE_ADDRESS=0x20;   /* send page address*/
     *(volatile unsigned short*)NAND_Flash_BASE_ADDRESS=0x0;    /* send block l address*/
     *(volatile unsigned short*)NAND_Flash_BASE_ADDRESS=0x0;   /* send block h address*/
    
     SET_ALE_L;     /*set ALE L*/
    
        
     /*wait R/#B to high*/
    do{}    
    while (!CHECK_BUSY);    
        
        
    #ifdef ECC
        RESET_ECC;
        EN_ECC; 
    #endif
        
    for (ReadCnt=0; ReadCnt< 512; ReadCnt+=2){
        *(volatile unsigned short*)(SRAM_BOOT_ADDR+ReadCnt)=*(volatile unsigned short*)NAND_Flash_BASE_ADDRESS;
    }
        
    #ifdef ECC
        DIS_ECC;
    
        getRedt[0]=*(volatile unsigned short*)NAND_Flash_BASE_ADDRESS;
        getRedt[1]=*(volatile unsigned short*)NAND_Flash_BASE_ADDRESS;
        getRedt[2]=*(volatile unsigned short*)NAND_Flash_BASE_ADDRESS;
            
        do{}
        while (!CHECK_ECC_READY);
        
        ECCRet=(unsigned short*)ECC_AREA0_COL_ADDR;
        
            
        for (i=0; i<3; i++)
                if (*ECCRet++ != getRedt[i])
                    return FLASH_ECC_ERROR;
      #endif
    
    JP_ADDR();
     
}