📄 init.lst
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C51 COMPILER V8.01 INIT 03/07/2007 14:09:12 PAGE 1
C51 COMPILER V8.01, COMPILATION OF MODULE INIT
OBJECT MODULE PLACED IN init.OBJ
COMPILER INVOKED BY: D:\Program Files\Keil\C51\BIN\C51.EXE init.c BROWSE DEBUG OBJECTEXTEND
line level source
1 #define INIT_GLOBAL
2 #include "includes.h"
3 //======================================================
4 void Init (void) {
5 1 InitPort();
6 1 Timer3_Init();
7 1 UART0_Init ();
8 1
9 1 // SmsSendFail = 0;
10 1 }
11 //=========================================================
12 void Timer3_Init (void)
13 {
14 1 // TMR3CN = 0x00; // Stop Timer3; Clear TF3;
15 1 // use SYSCLK/12 as timebase = 1S
16 1 // TMR3RL = -SYSCLK / 12 / 100; // Init reload values
17 1 TMR3RLL = -(SYSCLK / 12 / 100) & 0x00ff; // Timer 3 Reload Register Low Byte
18 1 TMR3RLH = -((SYSCLK / 12 / 100) & 0xff00)>>8; // Timer 3 Reload Register High Byte
19 1 TMR3H = 0xff; // Timer 3 High Byte
20 1 TMR3L = 0xff; // Timer 3 Low Byte
21 1 EIE2 |= 0x01; // Enable Timer3 interrupts
22 1 TMR3CN = 0x04; // Start Timer3
23 1 }
24 //========================================================
25 // Configure the UART using Timer1, for <baudrate> and 8-N-1.
26 void UART0_Init (void)
27 {
28 1 CKCON = 0x10; // Timer1 uses SYSCLK as time base
29 1 TMOD = 0x20; // TMOD: timer 1, mode 2, 8-bit reload
30 1 TH1 = -(SYSCLK/BAUDRATE/16); // set Timer1 reload value for baudrate
31 1 TL1 = 0xff;
32 1 TR1 = 1; // start Timer1
33 1 SCON0 = 0x50; // SCON: mode 1, 8-bit UART, enable RX
34 1 PCON |= 0x80; // SMOD = 1
35 1 TI0 = 0;
36 1
37 1 TCON = 0x40; // Timer Control Register
38 1
39 1 IE |= 0x10;
40 1 IP |= 0x10;
41 1 }
42 //==================================================================
43 void InitPort (void) {
44 1
45 1 //Local Variable Definitions
46 1 int n = 0;
47 1 //----------------------------------------------------------------
48 1 // Watchdog Timer Configuration
49 1 //
50 1 // WDTCN.[7:0]: WDT Control
51 1 // Writing 0xA5 enables and reloads the WDT.
52 1 // Writing 0xDE followed within 4 clocks by 0xAD disables the WDT
53 1 // Writing 0xFF locks out disable feature.
54 1 //
55 1 // WDTCN.[2:0]: WDT timer interval bits
C51 COMPILER V8.01 INIT 03/07/2007 14:09:12 PAGE 2
56 1 // NOTE! When writing interval bits, bit 7 must be a 0.
57 1 //
58 1 // Bit 2 | Bit 1 | Bit 0
59 1 //------------------------
60 1 // 1 | 1 | 1 Timeout interval = 1048576 x Tsysclk
61 1 // 1 | 1 | 0 Timeout interval = 262144 x Tsysclk
62 1 // 1 | 0 | 1 Timeout interval = 65636 x Tsysclk
63 1 // 1 | 0 | 0 Timeout interval = 16384 x Tsysclk
64 1 // 0 | 1 | 1 Timeout interval = 4096 x Tsysclk
65 1 // 0 | 1 | 0 Timeout interval = 1024 x Tsysclk
66 1 // 0 | 0 | 1 Timeout interval = 256 x Tsysclk
67 1 // 0 | 0 | 0 Timeout interval = 64 x Tsysclk
68 1 //
69 1 //------------------------
70 1
71 1 WDTCN = 0x07; // Watchdog Timer Control Register
72 1 WDTCN = 0xDE; // Disable WDT
73 1 WDTCN = 0xAD;
74 1
75 1 //----------------------------------------------------------------
76 1 // CROSSBAR REGISTER CONFIGURATION
77 1 //
78 1 // NOTE: The crossbar register should be configured before any
79 1 // of the digital peripherals are enabled. The pinout of the
80 1 // device is dependent on the crossbar configuration so caution
81 1 // must be exercised when modifying the contents of the XBR0,
82 1 // XBR1, and XBR2 registers. For detailed information on
83 1 // Crossbar Decoder Configuration, refer to Application Note
84 1 // AN001, "Configuring the Port I/O Crossbar Decoder".
85 1 //----------------------------------------------------------------
86 1
87 1 // Configure the XBRn Registers
88 1
89 1 XBR0 = 0x04; // XBAR0: Initial Reset Value
90 1 XBR1 = 0x00; // XBAR1: Initial Reset Value
91 1 XBR2 = 0x40; // XBAR2: Initial Reset Value
92 1 // Select Pin I/0
93 1
94 1 // NOTE: Some peripheral I/O pins can function as either inputs or
95 1 // outputs, depending on the configuration of the peripheral. By default,
96 1 // the configuration utility will configure these I/O pins as push-pull
97 1 // outputs.
98 1 // Port configuration (1 = Push Pull Output)
99 1 P0MDOUT = 0x01; // Output configuration for P0
100 1 P1MDOUT = 0x40;//0x00; // Output configuration for P1
101 1 P2MDOUT = 0x00; // Output configuration for P2
102 1 P3MDOUT = 0x00; // Output configuration for P3
103 1 P74OUT = 0x00; // Output configuration for P4-7
104 1
105 1 P1MDIN = 0xFF; // Input configuration for P1
106 1
107 1 // View port pinout
108 1
109 1 // The current Crossbar configuration results in the
110 1 // following port pinout assignment:
111 1 // Port 0
112 1 // P0.0 = UART TX0 (Push-Pull Output)
113 1 // P0.1 = UART RX0 (Open-Drain Output/Input)
114 1 // P0.2 = GP I/O (Open-Drain Output/Input)
115 1 // P0.3 = GP I/O (Open-Drain Output/Input)
116 1 // P0.4 = GP I/O (Open-Drain Output/Input)
117 1 // P0.5 = GP I/O (Open-Drain Output/Input)
C51 COMPILER V8.01 INIT 03/07/2007 14:09:12 PAGE 3
118 1 // P0.6 = GP I/O (Open-Drain Output/Input)
119 1 // P0.7 = GP I/O (Open-Drain Output/Input)
120 1
121 1 // Port 1
122 1 // P1.0 = GP I/O (Open-Drain Output/Input)(Digital)
123 1 // P1.1 = GP I/O (Open-Drain Output/Input)(Digital)
124 1 // P1.2 = GP I/O (Open-Drain Output/Input)(Digital)
125 1 // P1.3 = GP I/O (Open-Drain Output/Input)(Digital)
126 1 // P1.4 = GP I/O (Open-Drain Output/Input)(Digital)
127 1 // P1.5 = GP I/O (Open-Drain Output/Input)(Digital)
128 1 // P1.6 = GP I/O (Open-Drain Output/Input)(Digital)
129 1 // P1.7 = GP I/O (Open-Drain Output/Input)(Digital)
130 1
131 1 // Port 2
132 1 // P2.0 = GP I/O (Open-Drain Output/Input)
133 1 // P2.1 = GP I/O (Open-Drain Output/Input)
134 1 // P2.2 = GP I/O (Open-Drain Output/Input)
135 1 // P2.3 = GP I/O (Open-Drain Output/Input)
136 1 // P2.4 = GP I/O (Open-Drain Output/Input)
137 1 // P2.5 = GP I/O (Open-Drain Output/Input)
138 1 // P2.6 = GP I/O (Open-Drain Output/Input)
139 1 // P2.7 = GP I/O (Open-Drain Output/Input)
140 1
141 1 // Port 3
142 1 // P3.0 = GP I/O (Open-Drain Output/Input)
143 1 // P3.1 = GP I/O (Open-Drain Output/Input)
144 1 // P3.2 = GP I/O (Open-Drain Output/Input)
145 1 // P3.3 = GP I/O (Open-Drain Output/Input)
146 1 // P3.4 = GP I/O (Open-Drain Output/Input)
147 1 // P3.5 = GP I/O (Open-Drain Output/Input)
148 1 // P3.6 = GP I/O (Open-Drain Output/Input)
149 1 // P3.7 = GP I/O (Open-Drain Output/Input)
150 1
151 1 EMI0CF = 0x00; // External Memory Configuration Register
152 1
153 1 //----------------------------------------------------------------
154 1 // Comparators Register Configuration
155 1 //
156 1 // Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
157 1 //------------------------------------------------------------------
158 1 // R/W | R | R/W | R/W | R/W | R/W | R/W | R/W
159 1 //------------------------------------------------------------------
160 1 // Enable | Output | Rising | Falling| Positive | Negative
161 1 // | State | Edge | Edge | Hysterisis | Hysterisis
162 1 // | Flag | Int. | Int. | 00: Disable | 00: Disable
163 1 // | | Flag | Flag | 01: 5mV | 01: 5mV
164 1 // | | | | 10: 10mV | 10: 10mV
165 1 // | | | | 11: 20mV | 11: 20mV
166 1 // ----------------------------------------------------------------
167 1
168 1 CPT0CN = 0x00; // Comparator 0 Control Register
169 1 CPT1CN = 0x00; // Comparator 1 Control Register
170 1 //Comp1 marker
171 1 //----------------------------------------------------------------
172 1 // Oscillator Configuration
173 1 //----------------------------------------------------------------
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