hex.vhd

来自「在开发板上实现按键控制数码管实验」· VHDL 代码 · 共 29 行

library IEEE; 
use IEEE.std_logic_1164.all;
entity hex is
port ( data_in : in std_logic_vector (3 downto 0); 
       data_out : out std_logic_vector (6 downto 0) );
end entity;
architecture hex_arch of hex is 
begin 
   process(data_in) 
     begin 
           case data_in is 
                when "0000" => data_out <= "0111111"; -- 0 
                when "0001" => data_out <= "0000110"; -- 1 
                when "0010" => data_out <= "1011011"; -- 2 
                when "0011" => data_out <= "1001111"; -- 3 
                when "0100" => data_out <= "1100110"; -- 4 
                when "0101" => data_out <= "1101101"; -- 5 
                when "0110" => data_out <= "1111100"; -- 6 
                when "0111" => data_out <= "0000111"; -- 7 
                when "1000" => data_out <= "1111111"; -- 8 
                when "1001" => data_out <= "1100111"; -- 9 
                when "1010" => data_out <= "1110111"; -- A 
                when "1011" => data_out <= "1111100"; -- b 
                when "1100" => data_out <= "1011000"; -- c 
                when "1101" => data_out <= "1011110"; -- d 
                when "1110" => data_out <= "1111001"; -- E 
                when "1111" => data_out <= "1110001"; -- F 
                when others => NULL; end case; end process; 
end architecture;