svga.map.qmsg

在开发板上实现svga条形信号发生器的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 10:37:56 2007 " "Info: Processing started: Wed Jan 24 10:37:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SVGA -c SVGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SVGA -c SVGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SVGA.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SVGA.v" { { "Info" "ISGN_ENTITY_NAME" "1 SVGA " "Info: Found entity 1: SVGA" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 58 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SVGA_colour.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SVGA_colour.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SVGA_colour " "Info: Found entity 1: SVGA_colour" {  } { { "SVGA_colour.bdf" "" { Schematic "F:/PROJECT/Software/SVGA/SVGA_colour.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SVGA " "Info: Elaborating entity \"SVGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_FRONTPORCH SVGA.v(75) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(75): object \"H_FRONTPORCH\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 75 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_SYNCTIME SVGA.v(76) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(76): object \"H_SYNCTIME\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 76 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_BACKPORCH SVGA.v(77) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(77): object \"H_BACKPORCH\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 77 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_FRONTPORCH SVGA.v(83) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(83): object \"V_FRONTPORCH\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 83 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_SYNCTIME SVGA.v(84) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(84): object \"V_SYNCTIME\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 84 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_BACKPORCH SVGA.v(85) " "Warning (10036): Verilog HDL or VHDL warning at SVGA.v(85): object \"V_BACKPORCH\" assigned a value but never read" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 85 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 SVGA.v(98) " "Warning (10230): Verilog HDL assignment warning at SVGA.v(98): truncated value with size 32 to match size of target (11)" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 SVGA.v(119) " "Warning (10230): Verilog HDL assignment warning at SVGA.v(119): truncated value with size 32 to match size of target (11)" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 104 -1 0 } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 67 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 10:37:58 2007 " "Info: Processing ended: Wed Jan 24 10:37:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}