svga.tan.qmsg

在开发板上实现svga条形信号发生器的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register vcnt\[5\] register enable 58.21 MHz 17.18 ns Internal " "Info: Clock \"clock\" has Internal fmax of 58.21 MHz between source register \"vcnt\[5\]\" and destination register \"enable\" (period= 17.18 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.640 ns + Longest register register " "Info: + Longest register to register delay is 2.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vcnt\[5\] 1 REG LC_X29_Y16_N0 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vcnt[5] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.114 ns) 1.405 ns always4~64 2 COMB LC_X29_Y17_N4 1 " "Info: 2: + IC(1.291 ns) + CELL(0.114 ns) = 1.405 ns; Loc. = LC_X29_Y17_N4; Fanout = 1; COMB Node = 'always4~64'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.405 ns" { vcnt[5] always4~64 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.292 ns) 2.149 ns always4~65 3 COMB LC_X29_Y17_N2 1 " "Info: 3: + IC(0.452 ns) + CELL(0.292 ns) = 2.149 ns; Loc. = LC_X29_Y17_N2; Fanout = 1; COMB Node = 'always4~65'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.744 ns" { always4~64 always4~65 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 2.640 ns enable 4 REG LC_X29_Y17_N3 4 " "Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 2.640 ns; Loc. = LC_X29_Y17_N3; Fanout = 4; REG Node = 'enable'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { always4~65 enable } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.715 ns ( 27.08 % ) " "Info: Total cell delay = 0.715 ns ( 27.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.925 ns ( 72.92 % ) " "Info: Total interconnect delay = 1.925 ns ( 72.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.640 ns" { vcnt[5] always4~64 always4~65 enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.640 ns" { vcnt[5] always4~64 always4~65 enable } { 0.000ns 1.291ns 0.452ns 0.182ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.689 ns - Smallest " "Info: - Smallest clock skew is -5.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns enable 2 REG LC_X29_Y17_N3 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y17_N3; Fanout = 4; REG Node = 'enable'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clock enable } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock clock~out0 enable } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 8.651 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 8.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns hsyncint 2 REG LC_X16_Y13_N8 13 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X16_Y13_N8; Fanout = 13; REG Node = 'hsyncint'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.709 ns" { clock hsyncint } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.762 ns) + CELL(0.711 ns) 8.651 ns vcnt\[5\] 3 REG LC_X29_Y16_N0 12 " "Info: 3: + IC(4.762 ns) + CELL(0.711 ns) = 8.651 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.473 ns" { hsyncint vcnt[5] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.01 % ) " "Info: Total cell delay = 3.115 ns ( 36.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.536 ns ( 63.99 % ) " "Info: Total interconnect delay = 5.536 ns ( 63.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.651 ns" { clock hsyncint vcnt[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.651 ns" { clock clock~out0 hsyncint vcnt[5] } { 0.000ns 0.000ns 0.774ns 4.762ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock clock~out0 enable } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.651 ns" { clock hsyncint vcnt[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.651 ns" { clock clock~out0 hsyncint vcnt[5] } { 0.000ns 0.000ns 0.774ns 4.762ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 134 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.640 ns" { vcnt[5] always4~64 always4~65 enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.640 ns" { vcnt[5] always4~64 always4~65 enable } { 0.000ns 1.291ns 0.452ns 0.182ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock clock~out0 enable } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.651 ns" { clock hsyncint vcnt[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.651 ns" { clock clock~out0 hsyncint vcnt[5] } { 0.000ns 0.000ns 0.774ns 4.762ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock pixel\[0\] vcnt\[5\] 22.336 ns register " "Info: tco from clock \"clock\" to destination pin \"pixel\[0\]\" through register \"vcnt\[5\]\" is 22.336 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 8.651 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 8.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 13; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns hsyncint 2 REG LC_X16_Y13_N8 13 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X16_Y13_N8; Fanout = 13; REG Node = 'hsyncint'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.709 ns" { clock hsyncint } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.762 ns) + CELL(0.711 ns) 8.651 ns vcnt\[5\] 3 REG LC_X29_Y16_N0 12 " "Info: 3: + IC(4.762 ns) + CELL(0.711 ns) = 8.651 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.473 ns" { hsyncint vcnt[5] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.01 % ) " "Info: Total cell delay = 3.115 ns ( 36.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.536 ns ( 63.99 % ) " "Info: Total interconnect delay = 5.536 ns ( 63.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.651 ns" { clock hsyncint vcnt[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.651 ns" { clock clock~out0 hsyncint vcnt[5] } { 0.000ns 0.000ns 0.774ns 4.762ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.461 ns + Longest register pin " "Info: + Longest register to pin delay is 13.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vcnt\[5\] 1 REG LC_X29_Y16_N0 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y16_N0; Fanout = 12; REG Node = 'vcnt\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vcnt[5] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.442 ns) 2.042 ns LessThan11~216 2 COMB LC_X28_Y17_N1 1 " "Info: 2: + IC(1.600 ns) + CELL(0.442 ns) = 2.042 ns; Loc. = LC_X28_Y17_N1; Fanout = 1; COMB Node = 'LessThan11~216'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.042 ns" { vcnt[5] LessThan11~216 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 157 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.114 ns) 3.399 ns LessThan11~215 3 COMB LC_X28_Y15_N2 2 " "Info: 3: + IC(1.243 ns) + CELL(0.114 ns) = 3.399 ns; Loc. = LC_X28_Y15_N2; Fanout = 2; COMB Node = 'LessThan11~215'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.357 ns" { LessThan11~216 LessThan11~215 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 157 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.442 ns) 5.012 ns pixel~2667 4 COMB LC_X29_Y16_N8 1 " "Info: 4: + IC(1.171 ns) + CELL(0.442 ns) = 5.012 ns; Loc. = LC_X29_Y16_N8; Fanout = 1; COMB Node = 'pixel~2667'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.613 ns" { LessThan11~215 pixel~2667 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.122 ns) + CELL(0.442 ns) 6.576 ns pixel~2668 5 COMB LC_X27_Y16_N3 1 " "Info: 5: + IC(1.122 ns) + CELL(0.442 ns) = 6.576 ns; Loc. = LC_X27_Y16_N3; Fanout = 1; COMB Node = 'pixel~2668'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { pixel~2667 pixel~2668 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.442 ns) 7.425 ns pixel~2670 6 COMB LC_X27_Y16_N2 1 " "Info: 6: + IC(0.407 ns) + CELL(0.442 ns) = 7.425 ns; Loc. = LC_X27_Y16_N2; Fanout = 1; COMB Node = 'pixel~2670'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.849 ns" { pixel~2668 pixel~2670 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.912 ns) + CELL(2.124 ns) 13.461 ns pixel\[0\] 7 PIN PIN_4 0 " "Info: 7: + IC(3.912 ns) + CELL(2.124 ns) = 13.461 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'pixel\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.036 ns" { pixel~2670 pixel[0] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.006 ns ( 29.76 % ) " "Info: Total cell delay = 4.006 ns ( 29.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.455 ns ( 70.24 % ) " "Info: Total interconnect delay = 9.455 ns ( 70.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.461 ns" { vcnt[5] LessThan11~216 LessThan11~215 pixel~2667 pixel~2668 pixel~2670 pixel[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.461 ns" { vcnt[5] LessThan11~216 LessThan11~215 pixel~2667 pixel~2668 pixel~2670 pixel[0] } { 0.000ns 1.600ns 1.243ns 1.171ns 1.122ns 0.407ns 3.912ns } { 0.000ns 0.442ns 0.114ns 0.442ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.651 ns" { clock hsyncint vcnt[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.651 ns" { clock clock~out0 hsyncint vcnt[5] } { 0.000ns 0.000ns 0.774ns 4.762ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.461 ns" { vcnt[5] LessThan11~216 LessThan11~215 pixel~2667 pixel~2668 pixel~2670 pixel[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.461 ns" { vcnt[5] LessThan11~216 LessThan11~215 pixel~2667 pixel~2668 pixel~2670 pixel[0] } { 0.000ns 1.600ns 1.243ns 1.171ns 1.122ns 0.407ns 3.912ns } { 0.000ns 0.442ns 0.114ns 0.442ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "orient pixel\[1\] 19.797 ns Longest " "Info: Longest tpd from source pin \"orient\" to destination pin \"pixel\[1\]\" is 19.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns orient 1 PIN PIN_66 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_66; Fanout = 4; PIN Node = 'orient'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { orient } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.529 ns) + CELL(0.590 ns) 10.594 ns pixel~2671 2 COMB LC_X27_Y16_N4 2 " "Info: 2: + IC(8.529 ns) + CELL(0.590 ns) = 10.594 ns; Loc. = LC_X27_Y16_N4; Fanout = 2; COMB Node = 'pixel~2671'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.119 ns" { orient pixel~2671 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 12.426 ns pixel~2674 3 COMB LC_X28_Y15_N6 1 " "Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 12.426 ns; Loc. = LC_X28_Y15_N6; Fanout = 1; COMB Node = 'pixel~2674'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.832 ns" { pixel~2671 pixel~2674 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.114 ns) 13.777 ns pixel~2678 4 COMB LC_X27_Y16_N7 1 " "Info: 4: + IC(1.237 ns) + CELL(0.114 ns) = 13.777 ns; Loc. = LC_X27_Y16_N7; Fanout = 1; COMB Node = 'pixel~2678'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.351 ns" { pixel~2674 pixel~2678 } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.896 ns) + CELL(2.124 ns) 19.797 ns pixel\[1\] 5 PIN PIN_3 0 " "Info: 5: + IC(3.896 ns) + CELL(2.124 ns) = 19.797 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'pixel\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.020 ns" { pixel~2678 pixel[1] } "NODE_NAME" } } { "SVGA.v" "" { Text "F:/PROJECT/Software/SVGA/SVGA.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.893 ns ( 24.72 % ) " "Info: Total cell delay = 4.893 ns ( 24.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.904 ns ( 75.28 % ) " "Info: Total interconnect delay = 14.904 ns ( 75.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.797 ns" { orient pixel~2671 pixel~2674 pixel~2678 pixel[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "19.797 ns" { orient orient~out0 pixel~2671 pixel~2674 pixel~2678 pixel[1] } { 0.000ns 0.000ns 8.529ns 1.242ns 1.237ns 3.896ns } { 0.000ns 1.475ns 0.590ns 0.590ns 0.114ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 10:38:07 2007 " "Info: Processing ended: Wed Jan 24 10:38:07 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}