seg7_led.map.qmsg

三八译码器的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 15 15:44:20 2007 " "Info: Processing started: Mon Jan 15 15:44:20 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg7_led -c seg7_led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg7_led -c seg7_led" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_led.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg7_led.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 seg7_led " "Info: Found entity 1: seg7_led" {  } { { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hex-hex_arch " "Info: Found design unit 1: hex-hex_arch" {  } { { "hex.vhd" "" { Text "F:/elva/SOPCnew/38/hex.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hex " "Info: Found entity 1: hex" {  } { { "hex.vhd" "" { Text "F:/elva/SOPCnew/38/hex.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg7_led " "Info: Elaborating entity \"seg7_led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex hex:inst1 " "Info: Elaborating entity \"hex\" for hierarchy \"hex:inst1\"" {  } { { "seg7_led.bdf" "inst1" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { 88 288 472 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.tdf 1 1 " "Warning: Using design file lpm_counter0.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.tdf" "" { Text "F:/elva/SOPCnew/38/lpm_counter0.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst\"" {  } { { "seg7_led.bdf" "inst" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -120 304 448 -24 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.tdf" "lpm_counter_component" { Text "F:/elva/SOPCnew/38/lpm_counter0.tdf" 46 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.tdf" "" { Text "F:/elva/SOPCnew/38/lpm_counter0.tdf" 46 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_jig.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_jig.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_jig " "Info: Found entity 1: cntr_jig" {  } { { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_jig lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated " "Info: Elaborating entity \"cntr_jig\" for hierarchy \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "22 " "Info: Implemented 22 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 15 15:44:22 2007 " "Info: Processing ended: Mon Jan 15 15:44:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}