seg7_led.tan.qmsg

三八译码器的源代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "key1 " "Info: Assuming node \"key1\" is an undefined clock" {  } { { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -96 -88 80 -80 "key1" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key2 " "Info: Assuming node \"key2\" is an undefined clock" {  } { { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -32 -88 80 -16 "key2" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst2 " "Info: Detected gated clock \"inst2\" as buffer" {  } { { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -56 160 224 -8 "inst2" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key1 register register lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\] lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\] 275.03 MHz Internal " "Info: Clock \"key1\" Internal fmax is restricted to 275.03 MHz between source register \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\]\" and destination register \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.058 ns + Longest register register " "Info: + Longest register to register delay is 2.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\] 1 REG LC_X10_Y1_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.616 ns) + CELL(0.575 ns) 1.191 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X10_Y1_N6 2 " "Info: 2: + IC(0.616 ns) + CELL(0.575 ns) = 1.191 ns; Loc. = LC_X10_Y1_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.191 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.271 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|counter_cella2~COUTCOUT1_2 3 COMB LC_X10_Y1_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.271 ns; Loc. = LC_X10_Y1_N7; Fanout = 1; COMB Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|counter_cella2~COUTCOUT1_2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.058 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\] 4 REG LC_X10_Y1_N8 8 " "Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.058 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.787 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns ( 70.07 % ) " "Info: Total cell delay = 1.442 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.616 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.616 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.058 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.058 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } { 0.000ns 0.616ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 destination 7.922 ns + Shortest register " "Info: + Shortest clock path from clock \"key1\" to destination register is 7.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns key1 1 CLK PIN_68 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -96 -88 80 -80 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.114 ns) 2.820 ns inst2 2 COMB LC_X7_Y2_N2 4 " "Info: 2: + IC(1.231 ns) + CELL(0.114 ns) = 2.820 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.345 ns" { key1 inst2 } "NODE_NAME" } } { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -56 160 224 -8 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.391 ns) + CELL(0.711 ns) 7.922 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\] 3 REG LC_X10_Y1_N8 8 " "Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 7.922 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.102 ns" { inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns ( 29.03 % ) " "Info: Total cell delay = 2.300 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.622 ns ( 70.97 % ) " "Info: Total interconnect delay = 5.622 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 source 7.922 ns - Longest register " "Info: - Longest clock path from clock \"key1\" to source register is 7.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns key1 1 CLK PIN_68 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -96 -88 80 -80 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.114 ns) 2.820 ns inst2 2 COMB LC_X7_Y2_N2 4 " "Info: 2: + IC(1.231 ns) + CELL(0.114 ns) = 2.820 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.345 ns" { key1 inst2 } "NODE_NAME" } } { "seg7_led.bdf" "" { Schematic "F:/elva/SOPCnew/38/seg7_led.bdf" { { -56 160 224 -8 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.391 ns) + CELL(0.711 ns) 7.922 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\] 3 REG LC_X10_Y1_N6 10 " "Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 7.922 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_jig:auto_generated\|safe_q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.102 ns" { inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns ( 29.03 % ) " "Info: Total cell delay = 2.300 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.622 ns ( 70.97 % ) " "Info: Total interconnect delay = 5.622 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.058 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.058 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } { 0.000ns 0.616ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.922 ns" { key1 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.922 ns" { key1 key1~out0 inst2 lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.231ns 4.391ns } { 0.000ns 1.475ns 0.114ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3] } {  } {  } } } { "db/cntr_jig.tdf" "" { Text "F:/elva/SOPCnew/38/db/cntr_jig.tdf" 69 8 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}