seg7_led.tan.rpt

三八译码器的源代码

+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 15 15:44:31 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg7_led -c seg7_led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "key1" is an undefined clock
    Info: Assuming node "key2" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "inst2" as buffer
Info: Clock "key1" Internal fmax is restricted to 275.03 MHz between source register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]" and destination register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.058 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]'
            Info: 2: + IC(0.616 ns) + CELL(0.575 ns) = 1.191 ns; Loc. = LC_X10_Y1_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1'
            Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.271 ns; Loc. = LC_X10_Y1_N7; Fanout = 1; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2'
            Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.058 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
            Info: Total cell delay = 1.442 ns ( 70.07 % )
            Info: Total interconnect delay = 0.616 ns ( 29.93 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key1" to destination register is 7.922 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'
                Info: 2: + IC(1.231 ns) + CELL(0.114 ns) = 2.820 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
                Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 7.922 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
                Info: Total cell delay = 2.300 ns ( 29.03 % )
                Info: Total interconnect delay = 5.622 ns ( 70.97 % )
            Info: - Longest clock path from clock "key1" to source register is 7.922 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'
                Info: 2: + IC(1.231 ns) + CELL(0.114 ns) = 2.820 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
                Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 7.922 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]'
                Info: Total cell delay = 2.300 ns ( 29.03 % )
                Info: Total interconnect delay = 5.622 ns ( 70.97 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "key2" Internal fmax is restricted to 275.03 MHz between source register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]" and destination register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.058 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]'
            Info: 2: + IC(0.616 ns) + CELL(0.575 ns) = 1.191 ns; Loc. = LC_X10_Y1_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1'
            Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.271 ns; Loc. = LC_X10_Y1_N7; Fanout = 1; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2'
            Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.058 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
            Info: Total cell delay = 1.442 ns ( 70.07 % )
            Info: Total interconnect delay = 0.616 ns ( 29.93 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key2" to destination register is 8.174 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 1; CLK Node = 'key2'
                Info: 2: + IC(1.305 ns) + CELL(0.292 ns) = 3.072 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
                Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 8.174 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
                Info: Total cell delay = 2.478 ns ( 30.32 % )
                Info: Total interconnect delay = 5.696 ns ( 69.68 % )
            Info: - Longest clock path from clock "key2" to source register is 8.174 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 1; CLK Node = 'key2'
                Info: 2: + IC(1.305 ns) + CELL(0.292 ns) = 3.072 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
                Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 8.174 ns; Loc. = LC_X10_Y1_N6; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[1]'
                Info: Total cell delay = 2.478 ns ( 30.32 % )
                Info: Total interconnect delay = 5.696 ns ( 69.68 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]" (data pin = "key1", clock pin = "key1") is 0.506 ns
    Info: + Longest pin to register delay is 8.391 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'
        Info: 2: + IC(5.394 ns) + CELL(0.575 ns) = 7.444 ns; Loc. = LC_X10_Y1_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella0~COUTCOUT1_4'
        Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 7.524 ns; Loc. = LC_X10_Y1_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella1~COUTCOUT1'
        Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 7.604 ns; Loc. = LC_X10_Y1_N7; Fanout = 1; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUTCOUT1_2'
        Info: 5: + IC(0.000 ns) + CELL(0.787 ns) = 8.391 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
        Info: Total cell delay = 2.997 ns ( 35.72 % )
        Info: Total interconnect delay = 5.394 ns ( 64.28 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "key1" to destination register is 7.922 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'
        Info: 2: + IC(1.231 ns) + CELL(0.114 ns) = 2.820 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
        Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 7.922 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
        Info: Total cell delay = 2.300 ns ( 29.03 % )
        Info: Total interconnect delay = 5.622 ns ( 70.97 % )
Info: tco from clock "key2" to destination pin "seg7led1[5]" through register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[2]" is 13.268 ns
    Info: + Longest clock path from clock "key2" to source register is 8.174 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 1; CLK Node = 'key2'
        Info: 2: + IC(1.305 ns) + CELL(0.292 ns) = 3.072 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
        Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 8.174 ns; Loc. = LC_X10_Y1_N7; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[2]'
        Info: Total cell delay = 2.478 ns ( 30.32 % )
        Info: Total interconnect delay = 5.696 ns ( 69.68 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.870 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y1_N7; Fanout = 10; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[2]'
        Info: 2: + IC(0.609 ns) + CELL(0.590 ns) = 1.199 ns; Loc. = LC_X10_Y1_N9; Fanout = 1; COMB Node = 'hex:inst1|Mux1~3'
        Info: 3: + IC(1.563 ns) + CELL(2.108 ns) = 4.870 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'seg7led1[5]'
        Info: Total cell delay = 2.698 ns ( 55.40 % )
        Info: Total interconnect delay = 2.172 ns ( 44.60 % )
Info: th for register "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]" (data pin = "key1", clock pin = "key2") is 0.111 ns
    Info: + Longest clock path from clock "key2" to destination register is 8.174 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 1; CLK Node = 'key2'
        Info: 2: + IC(1.305 ns) + CELL(0.292 ns) = 3.072 ns; Loc. = LC_X7_Y2_N2; Fanout = 4; COMB Node = 'inst2'
        Info: 3: + IC(4.391 ns) + CELL(0.711 ns) = 8.174 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
        Info: Total cell delay = 2.478 ns ( 30.32 % )
        Info: Total interconnect delay = 5.696 ns ( 69.68 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.078 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_68; Fanout = 7; CLK Node = 'key1'
        Info: 2: + IC(5.397 ns) + CELL(0.423 ns) = 7.295 ns; Loc. = LC_X10_Y1_N7; Fanout = 1; COMB Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|counter_cella2~COUT'
        Info: 3: + IC(0.000 ns) + CELL(0.783 ns) = 8.078 ns; Loc. = LC_X10_Y1_N8; Fanout = 8; REG Node = 'lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_jig:auto_generated|safe_q[3]'
        Info: Total cell delay = 2.681 ns ( 33.19 % )
        Info: Total interconnect delay = 5.397 ns ( 66.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Jan 15 15:44:31 2007
    Info: Elapsed time: 00:00:01