system.h

基于Nios II的串口通信

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * F:\PROJECT\Software\demo4\software\board_kb_syslib\..\..\System_Core.ptf
 *
 * Generated: 2006-10-27 14:12:12.89
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "System_Core"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define UP3_BOARD
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x008008A0
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x008008A0
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x008008A0
#define ALT_CPU_FREQ 66600000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 2048
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x00800020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PIO

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x008008A0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0

/*
 * sys_clk_timer configuration
 *
 */

#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
#define SYS_CLK_TIMER_BASE 0x00800800
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_IRQ 1
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_PERIOD 1
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_FREQ 66600000

/*
 * high_res_timer configuration
 *
 */

#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"
#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"
#define HIGH_RES_TIMER_BASE 0x00800820
#define HIGH_RES_TIMER_SPAN 32
#define HIGH_RES_TIMER_IRQ 2
#define HIGH_RES_TIMER_ALWAYS_RUN 0
#define HIGH_RES_TIMER_FIXED_PERIOD 0
#define HIGH_RES_TIMER_SNAPSHOT 1
#define HIGH_RES_TIMER_PERIOD 100
#define HIGH_RES_TIMER_PERIOD_UNITS "us"
#define HIGH_RES_TIMER_RESET_OUTPUT 0
#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGH_RES_TIMER_MULT 0.000001
#define HIGH_RES_TIMER_FREQ 66600000

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x00000000
#define SDRAM_SPAN 8388608
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 200
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.4
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 0
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_CONTENTS_INFO "SIMDIR/sdram.dat 1147437419"

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x00800840
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0x0000
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_FREQ 66600000

/*
 * nCS0_pio configuration
 *
 */

#define NCS0_PIO_NAME "/dev/nCS0_pio"
#define NCS0_PIO_TYPE "altera_avalon_pio"
#define NCS0_PIO_BASE 0x00800850
#define NCS0_PIO_SPAN 16
#define NCS0_PIO_DO_TEST_BENCH_WIRING 0
#define NCS0_PIO_DRIVEN_SIM_VALUE 0x0000
#define NCS0_PIO_HAS_TRI 0
#define NCS0_PIO_HAS_OUT 1
#define NCS0_PIO_HAS_IN 0
#define NCS0_PIO_CAPTURE 0
#define NCS0_PIO_EDGE_TYPE "NONE"
#define NCS0_PIO_IRQ_TYPE "NONE"
#define NCS0_PIO_FREQ 66600000

/*
 * nOE_pio configuration
 *
 */

#define NOE_PIO_NAME "/dev/nOE_pio"
#define NOE_PIO_TYPE "altera_avalon_pio"
#define NOE_PIO_BASE 0x00800860
#define NOE_PIO_SPAN 16
#define NOE_PIO_DO_TEST_BENCH_WIRING 0
#define NOE_PIO_DRIVEN_SIM_VALUE 0x0000
#define NOE_PIO_HAS_TRI 0
#define NOE_PIO_HAS_OUT 1
#define NOE_PIO_HAS_IN 0
#define NOE_PIO_CAPTURE 0
#define NOE_PIO_EDGE_TYPE "NONE"
#define NOE_PIO_IRQ_TYPE "NONE"
#define NOE_PIO_FREQ 66600000

/*
 * nWE_pio configuration
 *
 */

#define NWE_PIO_NAME "/dev/nWE_pio"
#define NWE_PIO_TYPE "altera_avalon_pio"
#define NWE_PIO_BASE 0x00800870
#define NWE_PIO_SPAN 16
#define NWE_PIO_DO_TEST_BENCH_WIRING 0
#define NWE_PIO_DRIVEN_SIM_VALUE 0x0000
#define NWE_PIO_HAS_TRI 0
#define NWE_PIO_HAS_OUT 1
#define NWE_PIO_HAS_IN 0
#define NWE_PIO_CAPTURE 0
#define NWE_PIO_EDGE_TYPE "NONE"
#define NWE_PIO_IRQ_TYPE "NONE"
#define NWE_PIO_FREQ 66600000

/*
 * add_pio configuration
 *
 */

#define ADD_PIO_NAME "/dev/add_pio"
#define ADD_PIO_TYPE "altera_avalon_pio"
#define ADD_PIO_BASE 0x00800880
#define ADD_PIO_SPAN 16
#define ADD_PIO_DO_TEST_BENCH_WIRING 0
#define ADD_PIO_DRIVEN_SIM_VALUE 0x0000
#define ADD_PIO_HAS_TRI 0
#define ADD_PIO_HAS_OUT 1
#define ADD_PIO_HAS_IN 0
#define ADD_PIO_CAPTURE 0
#define ADD_PIO_EDGE_TYPE "NONE"
#define ADD_PIO_IRQ_TYPE "NONE"
#define ADD_PIO_FREQ 66600000

/*
 * shuju_pio configuration
 *
 */

#define SHUJU_PIO_NAME "/dev/shuju_pio"
#define SHUJU_PIO_TYPE "altera_avalon_pio"
#define SHUJU_PIO_BASE 0x00800890
#define SHUJU_PIO_SPAN 16
#define SHUJU_PIO_DO_TEST_BENCH_WIRING 0
#define SHUJU_PIO_DRIVEN_SIM_VALUE 0x0000
#define SHUJU_PIO_HAS_TRI 0
#define SHUJU_PIO_HAS_OUT 1
#define SHUJU_PIO_HAS_IN 0
#define SHUJU_PIO_CAPTURE 0
#define SHUJU_PIO_EDGE_TYPE "NONE"
#define SHUJU_PIO_IRQ_TYPE "NONE"
#define SHUJU_PIO_FREQ 66600000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      SDRAM

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */