anyka_cpu.h

启动代码

/** @file
 * @brief Define the register of ANYKA CPU
 *
 * Define the register address and bit map for system.
 * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.
 * @author 
 * @date 2006-01-16
 * @version 1.0
 * @note CPU AK3223M
 */

#ifndef _ANYKA_CPU_H_
#define _ANYKA_CPU_H_




/** @defgroup ANYKA_CPU  
 *	@ingroup M3PLATFORM
 */
/*@{*/


/** @{@name Base Address Define
 *	The base address of system memory space is define here. 
 *	Include memory assignment and module base address define.
 */
 /**Memory assignment*/
#define ROM_BASE_ADDR				0x00000000	//on chip rom
#define NORFLASH_BASE_ADDR			0x10000000	//NOR FLASH start address
#define CHIP_CONF_BASE_ADDR			0x20000000	// chip configurations
#define RAM_BASE_ADDR				0x30000000	// RAM start address
#define TRAM_BASE_ADDR				0x40000000	// on chip RAM start address
#define RAMLIKE_BASE_ADDR			0x50000000	// RAM-LIKE start address
#define NANDFLASH_BASE_ADDR			0x60000000	// NAND FLASH start address
#define USB_BASE_ADDR				0x70000000	// USB

/**Module base address of chip config*/
#define LCD_MODULE_BASE_ADDR		0x20010000	// LCD controller
#define IMAGE_MODULE_BASE_ADDR		0x20030000	// image sensor
#define VIDEO_MODULE_BASE_ADDR		0x20040000	// JPEG/H.263/MPEG4/MECodec
#define AUDIO_MODULE_BASE_ADDR		0x20050000	// audio processor(DSP?)
#define UART_MODULE_BASE_ADDR		0x20060000	// UART
#define MMC_MODULE_BASE_ADDR		0x20060000	// MMC
#define SD_MODULE_BASE_ADDR			0x20060000	// SD
#define SPI_MODULE_BASE_ADDR		0x20060000	// SPI
#define HOST_MODULE_BASE_ADDR		0x20080000	// host interface
#define NAND_MODULE_BASE_ADDR		0x20080000	// NAND FLASH controller
#define ADC_MODULE_BASE_ADDR    	0x20090000	// Analog 
#define GPIO_MODULE_BASE_ADDR		0x20090000	// GPIO registers
#define TIMER_MODULE_BASE_ADDR		0x20090000	// timer registers
#define FLASH_MODULE_BASE_ADDR		0x200A0000	// NOR FLASH controller
#define RAM_MODULE_BASE_ADDR		0x200B0000	// SDRAM/SSRAM/SRAM controller
#define DMA_MODULE_BASE_ADDR		0x200C0000	// DMA registers
#define CRC_MODULE_BASE_ADDR		0x200C0000	// CRC registers
#define RTC_MODULE_BASE_ADDR		0x200D0000	// RTC
/** @} */


/** @{@name System Control Register
 *	Define system control register here, include CLOCK/INT/RESET
 */
#define CLOCK_CTRL_REG				(CHIP_CONF_BASE_ADDR + 0x00000000)	// module clock control(switch)
#define RESET_CTRL_REG				(CHIP_CONF_BASE_ADDR + 0x00000004)	// module software reset control register
#define INT_STATUS_REG				(CHIP_CONF_BASE_ADDR + 0x00000014)		// module interrupt status register
#define STANDBY_REG					(CHIP_CONF_BASE_ADDR + 0x00000034)	// module standby register

#define IRQINT_MASK_REG				(CHIP_CONF_BASE_ADDR + 0x00000018)	// module IRQ interrupt mask register, 1: mask; 0:unmask(default);
#define FRQINT_MASK_REG				(CHIP_CONF_BASE_ADDR + 0x0000001C)	// module FRQ interrupt mask register, 1: mask; 0:unmask(default);

#define CLOCK_DIV_REG				(CHIP_CONF_BASE_ADDR + 0x00000020)	// clock divider register 1

/** @} */


/** @{@name System Control Register Bit map
 *	Define system control register bit map here,
 *	include CPU work mode, CLOCK control, INTERRUPT control
 */
/**CPU work mode */
#define ANYKA_CPU_Mode_USR		0x10
#define ANYKA_CPU_Mode_FIQ		0x11
#define ANYKA_CPU_Mode_IRQ		0x12
#define ANYKA_CPU_Mode_SVC		0x13
#define ANYKA_CPU_Mode_ABT		0x17
#define ANYKA_CPU_Mode_UNDEF	0x1B
#define ANYKA_CPU_Mode_SYS		0x1F		
#define ANYKA_CPU_I_Bit			0x80
#define ANYKA_CPU_F_Bit			0x40

/** CLOCK control register bit map*/
#define	CLOCK_CTRL_JPEG_MPEG			0x00000001
#define	CLOCK_CTRL_IMG_CAPTURE			0x00000002
#define	CLOCK_CTRL_SPI_CTL				0x00000004
#define	CLOCK_CTRL_LCD					0x00000008
#define	CLOCK_CTRL_AUDIO				0x00000010
#define	CLOCK_CTRL_USB					0x00000020
#define	CLOCK_CTRL_SD_MMC				0x00000040
#define	CLOCK_CTRL_HOST					0x00000080
#define	CLOCK_CTRL_GPIO_TIMER			0x00000100
#define	CLOCK_CTRL_RAM_ROM				0x00000200
#define	CLOCK_CTRL_JANUS				0x00000800
#define	CLOCK_CTRL_MOTION_ESTIMATION	0x00001000
#define	CLOCK_CTRL_CRC					0x00002000
#define	CLOCK_CTRL_RTC					0x00004000
#define	CLOCK_CTRL_UART0				0x00008000
#define	CLOCK_CTRL_UART1				0x00010000
#define	CLOCK_CTRL_UART2				0x00020000
#define	CLOCK_CTRL_USB_PLL				0x00040000
#define	CLOCK_CTRL_EN_SET				0x00080000

/** interrupt status register bit map*/
#define	INT_STATUS_LCD_BIT				0x00000002
#define	INT_STATUS_GUI_BIT				0x00000004
#define	INT_STATUS_CAMERA_BIT			0x00000008
#define	INT_STATUS_VIDEO_BIT			0x00000010
#define	INT_STATUS_AUDIO_BIT			0x00000020
#define	INT_STATUS_UART_MMC_BIT			0x00000040
#define	INT_STATUS_USBC_BIT				0x00000080
#define	INT_STATUS_HOST_BIT				0x00000100
#define	INT_STATUS_GPIO_TIMER_BIT		0x00000200
#define	INT_STATUS_FLASH_BIT			0x00000400
#define	INT_STATUS_RAM_BIT				0x00000800
#define	INT_STATUS_MMC_BIT				0x00001000
#define	INT_STATUS_UART1_BIT			0x00002000
#define	INT_STATUS_UART0_BIT			0x00004000
#define	INT_STATUS_SPI_BIT				0x00008000
#define	INT_STATUS_TIMER2_BIT			0x00010000
#define	INT_STATUS_TIMER1_BIT			0x00020000
#define	INT_STATUS_GPIO1SET_BIT			0x00040000
#define	INT_STATUS_GPIO2SET_BIT			0x00080000
#define	INT_STATUS_JPEG_MPEG_BIT		0x00100000
#define	INT_STATUS_MOTIONESTIMATION_BIT	0x00200000
#define	INT_STATUS_UART2_BIT			0x00400000
#define	INT_STATUS_CRC_DMA_BIT			0x00800000
#define	INT_STATUS_TIMER3_BIT			0x01000000
#define	INT_STATUS_TIMER4_BIT			0x02000000
#define	INT_STATUS_ADC2_BIT				0x04000000
#define	INT_STATUS_RTC_BIT				0x08000000
#define	INT_STATUS_USB_BIT				0x10000000
#define	INT_STATUS_USBDMA_BIT			0x20000000

/** IRQ interrupt mask register bit map*/
#define IRQ_MASK_LCD_BIT				0x00000002
#define IRQ_MASK_CAMERA_BIT				0x00000008
#define IRQ_MASK_JPEG_MPEG_MOTIONESTIMATION_BIT		0x00000010
#define IRQ_MASK_AUDIO_BIT				0x00000020
#define IRQ_MASK_UART_MMC_BIT			0x00000040
#define IRQ_MASK_USB_BIT				0x00000080
#define IRQ_MASK_HOST_BIT				0x00000100
#define IRQ_MASK_GPIO_TIMER_BIT			0x00000200
#define IRQ_MASK_FLASH_BIT				0x00000400
#define IRQ_MASK_RAM_BIT				0x00000800
#define IRQ_MASK_CRC_DMA_BIT			0x00001000
#define IRQ_MASK_RTC_BIT				0x00002000
/** @} */


/** @{@name LCD module register and bit map define
 */ 
#define LCD_CMD1_REG		(LCD_MODULE_BASE_ADDR | 0x0000)
#define LCD_CMD2_REG		(LCD_MODULE_BASE_ADDR | 0x0004)
#define LCD_GINFO_REG		(LCD_MODULE_BASE_ADDR | 0x0010)
#define LCD_CFBA_REG		(LCD_MODULE_BASE_ADDR | 0x0018)
#define LCD_MINFO_REG		(LCD_MODULE_BASE_ADDR | 0x001C)
#define LCD_Y1ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0020)
#define LCD_U1ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0024)
#define LCD_V1ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0028)
#define LCD_H1INFO1_REG		(LCD_MODULE_BASE_ADDR | 0x002C)
#define LCD_H1INFO2_REG		(LCD_MODULE_BASE_ADDR | 0x0030)
#define LCD_V1INFO1_REG		(LCD_MODULE_BASE_ADDR | 0x0034)
#define LCD_V1INFO2_REG		(LCD_MODULE_BASE_ADDR | 0x0038)
#define LCD_S1INFO_REG		(LCD_MODULE_BASE_ADDR | 0x003C)
#define LCD_Y2ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0040)
#define LCD_U2ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0044)
#define LCD_V2ADDR_REG		(LCD_MODULE_BASE_ADDR | 0x0048)
#define LCD_H2INFO1_REG		(LCD_MODULE_BASE_ADDR | 0x004C)
#define LCD_H2INFO2_REG		(LCD_MODULE_BASE_ADDR | 0x0050)
#define LCD_V2INFO1_REG		(LCD_MODULE_BASE_ADDR | 0x0054)
#define LCD_V2INFO2_REG		(LCD_MODULE_BASE_ADDR | 0x0058)
#define LCD_S2INFO_REG		(LCD_MODULE_BASE_ADDR | 0x005C)
#define LCD_DINFO1_REG		(LCD_MODULE_BASE_ADDR | 0x0060)
#define LCD_DINFO2_REG		(LCD_MODULE_BASE_ADDR | 0x0064)
#define LCD_STATUS_REG		(LCD_MODULE_BASE_ADDR | 0x0068)
#define LCD_READBACK_REG	(LCD_MODULE_BASE_ADDR | 0x006C)

/** @{@name LCD config define
 *	Define LCD controller config value and bit map
 *	
 */


#define LCD_MPU_INTERFACE	0x20000000	//LCD select MPU interface value
#define LCD_RGB_INTERFACE	0x10000000	//LCD select RGB interface value
#define MAIN_LCD_MPU_CMD	0x00000000	//master LCD command
#define MAIN_LCD_MPU_DATA	0x80000000	//master LCD data
#define SUB_LCD_MPU_CMD		0x10000000	//slaver LCD command
#define SUB_LCD_MPU_DATA	0x90000000	//slaver LCD data
/** @} */

/** @} */

/** @{@name IMAGE module register and bit map define
 */
#define IMG_CMD_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0000)
#define IMG_HINFO1_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0004)
#define IMG_HINFO2_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0008)
#define IMG_VINFO1_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x000C)
#define IMG_VINFO2_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0010)
#define IMG_SINFO_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0014)
#define IMG_YADDR_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0018)
#define IMG_UADDR_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x001C)
#define IMG_VADDR_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0020)
#define IMG_RGBADDR_ADDR	(IMAGE_MODULE_BASE_ADDR | 0x0024)
#define IMG_STATUS_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0028)
#define IMG_HISTA_ADDR		(IMAGE_MODULE_BASE_ADDR | 0x0060)