seg71.tan.rpt

这是一个很不错的CPLD数码管测试程序,从这个程序个大家得很多启发

; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[5]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[5]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[5]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[4]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[4]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[4]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[3]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[3]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[3]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[1]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[1]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[1]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[0]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[0]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[0]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; dataout[7] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; dataout[7] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; dataout[7] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; en[2]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; en[2]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; en[2]      ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[13] ; dataout[6] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[14] ; dataout[6] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:cnt_scan_rtl_0|dffs[15] ; dataout[6] ; clk        ;
+-------+--------------+------------+-------------------------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 14 11:12:47 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg71 -c seg71
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "lpm_counter:cnt_scan_rtl_0|dffs[0]" and destination register "lpm_counter:cnt_scan_rtl_0|dffs[15]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC81; Fanout = 21; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[15]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC81; Fanout = 21; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[15]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "dataout[4]" through register "lpm_counter:cnt_scan_rtl_0|dffs[13]" is 17.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC83; Fanout = 23; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[13]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC83; Fanout = 23; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[13]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'reduce_or~388'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'dataout[4]'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 14 11:12:48 2005
    Info: Elapsed time: 00:00:01