seg71.map.rpt

这是一个很不错的CPLD数码管测试程序,从这个程序个大家得很多启发

; lpm_counter.tdf                  ; yes             ; Megafunction           ; e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf                        ;
; lpm_constant.inc                 ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/lpm_constant.inc                       ;
; lpm_decode.inc                   ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/lpm_decode.inc                         ;
; lpm_add_sub.inc                  ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/lpm_add_sub.inc                        ;
; cmpconst.inc                     ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/cmpconst.inc                           ;
; lpm_compare.inc                  ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/lpm_compare.inc                        ;
; lpm_counter.inc                  ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/lpm_counter.inc                        ;
; dffeea.inc                       ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/dffeea.inc                             ;
; alt_synch_counter.inc            ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/alt_synch_counter.inc                  ;
; alt_synch_counter_f.inc          ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/alt_synch_counter_f.inc                ;
; alt_counter_f10ke.inc            ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.inc                  ;
; alt_counter_stratix.inc          ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/alt_counter_stratix.inc                ;
; aglobal60.inc                    ; yes             ; Other                  ; e:/altera/quartus60/libraries/megafunctions/aglobal60.inc                          ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+----------------------+-------------------------------------+
; Resource             ; Usage                               ;
+----------------------+-------------------------------------+
; Logic cells          ; 32                                  ;
; Total registers      ; 16                                  ;
; I/O pins             ; 18                                  ;
; Maximum fan-out node ; lpm_counter:cnt_scan_rtl_0|dffs[13] ;
; Maximum fan-out      ; 17                                  ;
; Total fan-out        ; 213                                 ;
; Average fan-out      ; 4.26                                ;
+----------------------+-------------------------------------+


+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                     ;
+---------------------------------+------------+------+-----------------------------------+
; Compilation Hierarchy Node      ; Macrocells ; Pins ; Full Hierarchy Name               ;
+---------------------------------+------------+------+-----------------------------------+
; |seg71                          ; 32         ; 18   ; |seg71                            ;
;    |lpm_counter:cnt_scan_rtl_0| ; 16         ; 0    ; |seg71|lpm_counter:cnt_scan_rtl_0 ;
+---------------------------------+------------+------+-----------------------------------+


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_scan_rtl_0 ;
+------------------------+-------------------+--------------------------------+
; Parameter Name         ; Value             ; Type                           ;
+------------------------+-------------------+--------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                 ;
; LPM_WIDTH              ; 16                ; Untyped                        ;
; LPM_DIRECTION          ; UP                ; Untyped                        ;
; LPM_MODULUS            ; 0                 ; Untyped                        ;
; LPM_AVALUE             ; UNUSED            ; Untyped                        ;
; LPM_SVALUE             ; UNUSED            ; Untyped                        ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                        ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                        ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                        ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH             ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK             ;
; CARRY_CNT_EN           ; SMART             ; Untyped                        ;
; LABWIDE_SCLR           ; ON                ; Untyped                        ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                        ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                        ;
+------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Dec 20 20:14:53 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg71 -c seg71
Info: Found 1 design units, including 1 entities, in source file seg71.v
    Info: Found entity 1: seg71
Info: Elaborating entity "seg71" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at seg71.v(26): truncated value with size 32 to match size of target (16)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: "cnt_scan[0]~0"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:cnt_scan_rtl_0"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 50 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 32 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Dec 20 20:14:54 2006
    Info: Elapsed time: 00:00:01