key1.map.qmsg

Altera CPLD矩阵键盘一个很不错的Altera芯片程序

{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|key1\|scan_key 16 " "Info: State machine \"\|key1\|scan_key\" contains 16 states" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|key1\|scan_key " "Info: Selected Auto state machine encoding method for state machine \"\|key1\|scan_key\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|key1\|scan_key " "Info: Encoding result for state machine \"\|key1\|scan_key\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key1\|scan_key.state_bit_3 " "Info: Encoded state bit \"key1\|scan_key.state_bit_3\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key1\|scan_key.state_bit_2 " "Info: Encoded state bit \"key1\|scan_key.state_bit_2\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key1\|scan_key.state_bit_1 " "Info: Encoded state bit \"key1\|scan_key.state_bit_1\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key1\|scan_key.state_bit_0 " "Info: Encoded state bit \"key1\|scan_key.state_bit_0\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0000 0000 " "Info: State \"\|key1\|scan_key.0000\" uses code string \"0000\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1110 0010 " "Info: State \"\|key1\|scan_key.1110\" uses code string \"0010\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1101 0011 " "Info: State \"\|key1\|scan_key.1101\" uses code string \"0011\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1100 0110 " "Info: State \"\|key1\|scan_key.1100\" uses code string \"0110\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1011 0100 " "Info: State \"\|key1\|scan_key.1011\" uses code string \"0100\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1010 0101 " "Info: State \"\|key1\|scan_key.1010\" uses code string \"0101\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1001 0111 " "Info: State \"\|key1\|scan_key.1001\" uses code string \"0111\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1000 1000 " "Info: State \"\|key1\|scan_key.1000\" uses code string \"1000\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0111 1001 " "Info: State \"\|key1\|scan_key.0111\" uses code string \"1001\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0110 1010 " "Info: State \"\|key1\|scan_key.0110\" uses code string \"1010\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0101 1011 " "Info: State \"\|key1\|scan_key.0101\" uses code string \"1011\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0100 1100 " "Info: State \"\|key1\|scan_key.0100\" uses code string \"1100\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0011 1101 " "Info: State \"\|key1\|scan_key.0011\" uses code string \"1101\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0010 1110 " "Info: State \"\|key1\|scan_key.0010\" uses code string \"1110\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0001 1111 " "Info: State \"\|key1\|scan_key.0001\" uses code string \"1111\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1111 0001 " "Info: State \"\|key1\|scan_key.1111\" uses code string \"0001\"" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "52 " "Info: Implemented 52 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 04 16:18:52 2007 " "Info: Processing ended: Sun Feb 04 16:18:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}