📄 source7.ucp
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.line 1 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc"
;branch if the specified signal is deasserted.if the signal is asserted,clear the signal and do not
;branch
.xfer_order $xfer0 $xfer1 $xfer2 $xfer3
sram[read, $xfer0, op1, 0, 2], sig_done
wait#:
br_!signal[sram, wait#], guess_branch
nop;delay 1 cycle before reading $xfer0
alu[gpr0,0,b,$xfer0];valid data is written to gpr0
alu[gpr1,0,b,$xfer1];valid data is written to gpr0
self#:
br[self#]
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