source7.uc

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· UC 代码 · 共 11 行

;branch if the specified signal is deasserted.if the signal is asserted,clear the signal and do not
;branch
.xfer_order $xfer0 $xfer1 $xfer2 $xfer3
sram[read, $xfer0, op1, 0, 2], sig_done
wait#:
br_!signal[sram, wait#], guess_branch
nop;delay 1 cycle before reading $xfer0
alu[gpr0,0,b,$xfer0];valid data is written to  gpr0
alu[gpr1,0,b,$xfer1];valid data is written to  gpr0
self#:
br[self#]