source7.list

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· LIST 代码 · 共 66 行

+version:  7/2/1998
+switches:  
+uca_version: 2.0.83
+uca_date: Aug  2 2001 00:02:16
+current_date: Tue Jul 02 10:21:10 2002

.cpu_version 0x00000001 1 15

.%num_contexts 4

.%local_mem0_mode rel
.%local_mem1_mode rel

:self# 5
:wait# 1
*-- no_destination F0
*gpr1 gpr_b_rel D0
*op1 gpr_a_rel C1
*gpr0 gpr_a_rel C0
*$xfer3 sram_rel E3
*$xfer2 sram_rel E2
*$xfer1 sram_rel E1
*$xfer0 sram_rel E0
.0 A4041038 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 3 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	;branch if the specified signal is deasserted.if the signal is asserted,clear the signal and do not
	;branch
	.xfer_order $xfer0 $xfer1 $xfer2 $xfer3
	.%line 4 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	sram[read, $xfer0, op1, 0, 2], sig_done
.1 FE400097 common_code
	.%line 5 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	wait#:
	.%line 6 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	br_!signal[sram, wait#], guess_branch
.2 DE000000 common_code
	.%line 7 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	nop;delay 1 cycle before reading $xfer0
.3 00000820 common_code
	.%line 8 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	alu_shf[gpr0,0,b,$xfer0,0];valid data is written to  gpr0
.4 020008A0 common_code
	.%line 9 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	alu_shf[gpr1,0,b,$xfer1,0];valid data is written to  gpr0
.5 F8000287 common_code
	.%line 10 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	self#:
	.%line 11 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南3之demo工程\demo7\demo7\Source7.uc" 1
	br[self#]
+ucode_end



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