source1.uc

Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与Demo Code.

;Reference Instructions
;TA
;sram (sig_done & br_!signal)
.xfer_order $xfer0 $xfer1 $xfer2 $xfer3 ;allocate 4 continuous SRAM XEFERs 
immed[$xfer0,0xffff1111]
immed[$xfer1,0xffff2222]
immed[$xfer2,0xffff3333]
immed[$xfer3,0xffff4444]
immed[base,0]
immed[offset,0]
sram[write, $xfer0, base, offset, 4], sig_done ;write the 4 continuous SRAM XEFERs(starting at $xfer0) to SRAM (starting address is base+offset)
wait#:
br_!signal[sram, wait#], guess_branch,defer[1]
nop
self#:
br[self#]


//demo(1):         (GUI:Memory Watch)
//sram write       Burst Freq. = 1/2 uEng Freq.
//
//demo(2):         (GUI: History->Queues ,Queue Status)  
//watching sram order queue 
//
//demo(3):      
//sig_done & br!=signal 
//
//demo(4):         (GUI: project->System Configuration)
//flowthrough SSRAM - sram instruction is issued at cycle 10,isserted into Order Queue at cycle 13,sram[0] is written at cycle 23
//pipeline SSRAM    - sram instruction is issued at cycle 10,isserted into Order Queue at cycle 13,sram[0] is written at cycle 25 ,2 cycles delayed than flowthru SSRAM